From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Wed, 27 Sep 2023 07:43:17 +0000 (+0100)
Subject: Added english language description and brackets for lmw instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=532e126976288c799bdc8503c5d9808f34a2b6ac;p=openpower-isa.git

Added english language description and brackets for lmw instruction
---

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 233b45ed..bcde4ec0 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -744,7 +744,7 @@ Special Registers Altered:
 
 # Load Multiple Word
 
-DQ-Form
+D-Form
 
 * lmw RT,D(RA)
 
@@ -758,6 +758,22 @@ Pseudo-code:
         r <- r + 1
         EA <- EA + 4
 
+Description:
+
+    Let n = (32-RT). Let the effective address (EA) be the
+    sum (RA|0)+ D.
+
+    n consecutive words starting at EA are loaded into the
+    low-order 32 bits of GPRs RT through 31. The
+    high-order 32 bits of these GPRs are set to zero.
+
+    If RA is in the range of registers to be loaded, including
+    the case in which RA=0, the instruction form is invalid.
+
+    This instruction is not supported in Little-Endian mode.
+    If it is executed in Little-Endian mode, the system align-
+    ment error handler is invoked.
+
 Special Registers Altered:
 
     None