From: Kenneth Graunke Date: Wed, 24 May 2017 04:30:02 +0000 (-0700) Subject: genxml: Add Gen9 CACHE_MODE_1 definitons. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53368b008e62ddfbda896b5f0d3c69415052a845;p=mesa.git genxml: Add Gen9 CACHE_MODE_1 definitons. These were already in gen8.xml but not gen9.xml. There are a few new fields and a couple that have changed. These are all documented in the Skylake PRM, Volume 2c Command Reference: Registers, Part 1. Reviewed-by: Plamena Manolova Acked-by: Jason Ekstrand --- diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index a2c2020d140..3e9e88e219a 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -3682,6 +3682,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +