From: Samuel Pitoiset Date: Tue, 30 Jun 2020 16:45:08 +0000 (+0200) Subject: radv: fix wide points and lines X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53372175c9b42605cc411e45d100245ba3b93e2e;p=mesa.git radv: fix wide points and lines The maximum value for both points and lines is 65536. This doesn't fix anything known (just found this while looking in that area). Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 31930d73843..7b0afef9c90 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1266,7 +1266,7 @@ radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer) unsigned width = cmd_buffer->state.dynamic.line_width * 8; radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL, - S_028A08_WIDTH(CLAMP(width, 0, 0xFFF))); + S_028A08_WIDTH(CLAMP(width, 0, 0xFFFF))); } static void diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 4401f39e77c..e8324162296 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -1467,8 +1467,8 @@ void radv_GetPhysicalDeviceProperties( .maxCullDistances = 8, .maxCombinedClipAndCullDistances = 8, .discreteQueuePriorities = 2, - .pointSizeRange = { 0.0, 8192.0 }, - .lineWidthRange = { 0.0, 8192.0 }, + .pointSizeRange = { 0.0, 8191.875 }, + .lineWidthRange = { 0.0, 8191.875 }, .pointSizeGranularity = (1.0 / 8.0), .lineWidthGranularity = (1.0 / 8.0), .strictLines = false, /* FINISHME */ diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index e6a3bcd45a2..4b73bc513b5 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -484,7 +484,7 @@ si_emit_graphics(struct radv_device *device, radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1); radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) | - S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); + S_028A04_MAX_SIZE(radv_pack_float_12p4(8191.875/2))); if (!has_clear_state) { radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,