From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 6 Apr 2020 16:15:03 +0000 (+0000)
Subject: sort-of got layout positions ok
X-Git-Tag: partial-core-ls180-gdsii~145
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53376f8c81fc606caf81913d042799fa8001db58;p=soclayout.git

sort-of got layout positions ok
---

diff --git a/experiments7/doAlu16.py b/experiments7/doAlu16.py
index c2fdcde..427b16f 100755
--- a/experiments7/doAlu16.py
+++ b/experiments7/doAlu16.py
@@ -73,7 +73,7 @@ class ALU16(Module):
     def build(self):
 
         h_margin = 25.0
-        v_margin = 50.0
+        v_margin = 10.0
 
         if not self.build_submodules():
             return False
@@ -94,15 +94,15 @@ class ALU16(Module):
             ])) + 2*v_margin
 
             # experiment, over-ride
-            width = 1500
-            height = 450
+            width = 1300
+            height = 370
 
             self.ab = Box(0, 0, self.to_dbu(width), self.to_dbu(height))
 
             add_wid = self.from_dbu(add.ab.getWidth())
             sub_ht = self.from_dbu(sub.ab.getHeight())
             self.place_submodule(add, h_margin, v_margin+add_wid)
-            self.place_submodule(sub, width-sub.ab_width-h_margin+sub_ht-25,
+            self.place_submodule(sub, width-sub.ab_width-h_margin+sub_ht-45,
                                       v_margin)
 
             # TODO: replace with some form of lazy evaluation?
@@ -128,8 +128,8 @@ class ALU16(Module):
             self.to_dbu((width+self.ab_width)/2 + h_margin),
             self.to_dbu(height - v_margin)
         )
-        self.ab = Box(self.to_dbu(550), self.to_dbu(25),
-                      self.to_dbu(1000), self.to_dbu(450))
+        self.ab = Box(self.to_dbu(450), self.to_dbu(15),
+                      self.to_dbu(835), self.to_dbu(370))
         self.place() # place only
 
         # then route (globally)
@@ -181,12 +181,12 @@ def ScriptMain(editor=None, **kwargs):
     alu16 = ALU16(
         'alu16', editor, submodules=[add, sub],
         north_pins=[
-            {'net': 'o({})', 'x': 50.0, 'delta': 60.0, 'repeat': BIT_WIDTH},
+            {'net': 'o({})', 'x': 500.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
             {'net': 'op'},
         ],
         south_pins=[
-            {'net': 'a({})', 'x': 50.0, 'delta': 60.0, 'repeat': BIT_WIDTH},
-            {'net': 'b({})', 'x': 80.0, 'delta': 60.0, 'repeat': BIT_WIDTH},
+            {'net': 'a({})', 'x': 500.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
+            {'net': 'b({})', 'x': 700.0, 'delta': 10.0, 'repeat': BIT_WIDTH},
         ],
         west_pins=[
             {'net': 'rst', 'y': 140.0, 'layer': 'METAL2'},