From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Sep 2019 22:46:15 +0000 (-0700)
Subject: Perform D replacement properly
X-Git-Tag: working-ls180~1039^2~172
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5344bfe637e0c8d527f94f615e4ed8704c358cf8;p=yosys.git

Perform D replacement properly
---

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 547073aa6..ba8a1de05 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -144,13 +144,22 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
 			cell->setParam("\\BREG", 1);
 		}
 		if (st.ffD) {
+			SigSpec D_ = cell->getPort("\\D");
+			SigSpec D = st.ffB->getPort("\\D");
+			SigSpec Q = st.ffB->getPort("\\Q");
+			D_.replace(Q, D);
+
 			if (st.ffDmux) {
+				SigSpec Y = st.ffDmux->getPort("\\Y");
+				SigSpec AB = st.ffDmux->getPort(st.ffDenpol ? "\\B" : "\\A");
 				SigSpec S = st.ffDmux->getPort("\\S");
-				cell->setPort("\\CED", st.ffBenpol ? S : pm.module->Not(NEW_ID, S));
+				D_.replace(Y, AB);
+
+				cell->setPort("\\CED", st.ffDenpol ? S : pm.module->Not(NEW_ID, S));
 			}
 			else
 				cell->setPort("\\CED", State::S1);
-			cell->setPort("\\D", st.sigD);
+			cell->setPort("\\D", D_);
 
 			cell->setParam("\\DREG", 1);
 		}
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 6cc42e2e1..9e4738c88 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -286,11 +286,6 @@ match ffDmux
 	optional
 endmatch
 
-code sigD
-	if (ffDmux)
-		sigD.replace(port(ffDmux, \Y), port(ffDmux, ffDenpol ? \B : \A));
-endcode
-
 match ffMmux
 	if param(dsp, \MREG).as_int() == 0
 	if nusers(sigM) == 2