From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sun, 12 May 2013 13:58:08 +0000 (+0200)
Subject: First video mixing working (hacky)
X-Git-Tag: 24jan2021_ls180~2931
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=534dec62eb3056a515428f305bcf70d57e7e02da;p=litex.git

First video mixing working (hacky)
---

diff --git a/milkymist/dvisampler/analysis.py b/milkymist/dvisampler/analysis.py
index 4361f0ab..d402ce08 100644
--- a/milkymist/dvisampler/analysis.py
+++ b/milkymist/dvisampler/analysis.py
@@ -136,7 +136,7 @@ class FrameExtraction(Module):
 			vsync_r.eq(self.vsync)
 		]
 
-		fifo = AsyncFIFO(layout_len(frame_layout), 256)
+		fifo = AsyncFIFO(layout_len(frame_layout), 512)
 		self.add_submodule(fifo, {"write": "pix", "read": "sys"})
 		self.comb += [
 			fifo.we.eq(fifo_stb),
diff --git a/milkymist/framebuffer/lib.py b/milkymist/framebuffer/lib.py
index e85ed9df..7fa5c9bd 100644
--- a/milkymist/framebuffer/lib.py
+++ b/milkymist/framebuffer/lib.py
@@ -129,7 +129,7 @@ class FIFO(Module):
 		###
 
 		data_width = 2+2*3*bpc_dac
-		fifo = AsyncFIFO(data_width, 256)
+		fifo = AsyncFIFO(data_width, 512)
 		self.add_submodule(fifo, {"write": "sys", "read": "vga"})
 		fifo_in = self.dac.payload
 		fifo_out = Record(dac_layout)
diff --git a/top.py b/top.py
index 7adb852a..029a02fd 100644
--- a/top.py
+++ b/top.py
@@ -13,7 +13,7 @@ from cif import get_macros
 
 version = get_macros("common/version.h")["VERSION"][1:-1]
 
-clk_freq = (83 + Fraction(1, 3))*1000000
+clk_freq = (62 + Fraction(1, 2))*1000000
 sram_size = 4096 # in bytes
 l2_size = 8192 # in bytes
 
@@ -93,10 +93,10 @@ class SoC(Module):
 		#
 		self.submodules.asmicon = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
 		asmiport_wb = self.asmicon.hub.get_port()
-		asmiport_fb0 = self.asmicon.hub.get_port(2)
-		asmiport_fb1 = self.asmicon.hub.get_port(2)
-		asmiport_dvi0 = self.asmicon.hub.get_port(2)
-		asmiport_dvi1 = self.asmicon.hub.get_port(2)
+		asmiport_fb0 = self.asmicon.hub.get_port(4)
+		asmiport_fb1 = self.asmicon.hub.get_port(4)
+		asmiport_dvi0 = self.asmicon.hub.get_port(4)
+		asmiport_dvi1 = self.asmicon.hub.get_port(4)
 		self.asmicon.finalize()
 		
 		#