From: whitequark <whitequark@whitequark.org>
Date: Sat, 22 Dec 2018 00:53:05 +0000 (+0000)
Subject: compat: fix confusing naming for memory port address signal.
X-Git-Tag: working~151
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5361b4c22b0f71d461dd195b347afb69e9154ced;p=nmigen.git

compat: fix confusing naming for memory port address signal.
---

diff --git a/nmigen/compat/fhdl/specials.py b/nmigen/compat/fhdl/specials.py
index 0c27c57..5449ba6 100644
--- a/nmigen/compat/fhdl/specials.py
+++ b/nmigen/compat/fhdl/specials.py
@@ -64,6 +64,7 @@ class CompatMemory(NativeMemory):
             we_granularity = None
         assert mode != NO_CHANGE
         rdport = self.read_port(synchronous=not async_read, transparent=mode == WRITE_FIRST)
+        rdport.addr.name = "{}_addr".format(self.name)
         adr = rdport.addr
         dat_r = rdport.data
         if write_capable: