From: Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com>
Date: Fri, 14 Jun 2019 09:39:24 +0000 (+0200)
Subject: Prepare for situation when port of the signal cannot be found
X-Git-Tag: working-ls180~1239^2~4^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53695e6729e8ae603be7e7cd9bc8b29758d61a11;p=yosys.git

Prepare for situation when port of the signal cannot be found
---

diff --git a/kernel/algo.h b/kernel/algo.h
index 9626c780e..f029ad6ab 100644
--- a/kernel/algo.h
+++ b/kernel/algo.h
@@ -58,10 +58,14 @@ struct Netlist {
 		return sigbit_driver_map.at(sig);
 	}
 
-	RTLIL::SigBit& driver_port(RTLIL::SigBit sig)
+	RTLIL::SigSpec driver_port(RTLIL::SigBit sig)
 	{
 		RTLIL::Cell *cell = driver_cell(sig);
 
+		if (!cell) {
+			return RTLIL::SigSpec();
+		}
+
 		for (auto &port : cell->connections_) {
 			if (ct.cell_output(cell->type, port.first)) {
 				RTLIL::SigSpec port_sig = sigmap(port.second);
@@ -72,6 +76,8 @@ struct Netlist {
 				}
 			}
 		}
+
+		return RTLIL::SigSpec();
 	}
 
 	void setup_netlist(RTLIL::Module *module, const CellTypes &ct)
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 41bbdcd57..cf89ac096 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -503,7 +503,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 			// If the register bit cannot change, we can replace it with a constant
 			if (!counter_example_found) {
 
-				RTLIL::SigBit &driver_port = net.driver_port(q_sigbit);
+				RTLIL::SigSpec driver_port = net.driver_port(q_sigbit);
 				RTLIL::Wire *dummy_wire = mod->addWire(NEW_ID, 1);
 
 				for (auto &conn : mod->connections_)