From: lkcl <lkcl@web>
Date: Fri, 18 Dec 2020 00:21:57 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1223
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53716ceb746a972f23b55c1fc0c06ca77526a35f;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 67ea3d575..857fc0ab4 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -560,6 +560,8 @@ Note: CR[-8] through CR[-1] are not part of OpenPower v3.1, they are the MSB hal
 
 # Register Profiles
 
+**NOTE THIS TABKE SHOULD NO LONGER BE HAND EDITED** see <https://bugs.libre-soc.org/show_bug.cgi?id=548> for details.
+
 Instructions are broken down by Register Profiles as listed in the following auto-generated page:
 [[opcode_regs_deduped]].  "Non-SV" indicates that the operations with this Register Profile cannot be Vectorised (mtspr, bc, dcbz, twi)