From: Luke Kenneth Casson Leighton Date: Tue, 19 Feb 2019 08:23:20 +0000 (+0000) Subject: INF + -INF bug X-Git-Tag: ls180-24jan2020~1870 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5371cd400205c92593911ff94b4d5e050634bd5c;p=ieee754fpu.git INF + -INF bug --- diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index 26c779ff..e1d0b40c 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -66,7 +66,7 @@ class FPADD(FPBase): m.d.sync += z.inf(a.s) # if a is inf and signs don't match return NaN with m.If((b.e == b.P128) & (a.s != b.s)): - m.d.sync += z.nan(b.s) + m.d.sync += z.nan(1) # if b is inf return inf with m.Elif(b.is_inf()): diff --git a/src/add/test_add.py b/src/add/test_add.py index d97ade8d..bb419049 100644 --- a/src/add/test_add.py +++ b/src/add/test_add.py @@ -13,6 +13,9 @@ from unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan, run_edge_cases, run_corner_cases) def testbench(dut): + yield from check_case(dut, 0xFF800000, 0x7F800000, 0xFFC00000) + #yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000) + yield from check_case(dut, 0x7F800000, 0xFF800000, 0xFFC00000) yield from check_case(dut, 0x42540000, 0xC2540000, 0x00000000) yield from check_case(dut, 0xC2540000, 0x42540000, 0x00000000) yield from check_case(dut, 0xfe34f995, 0xff5d59ad, 0xff800000) @@ -35,8 +38,6 @@ def testbench(dut): yield from check_case(dut, 0x00000000, 0xFF800000, 0xFF800000) yield from check_case(dut, 0x7F800000, 0x7F800000, 0x7F800000) yield from check_case(dut, 0xFF800000, 0xFF800000, 0xFF800000) - yield from check_case(dut, 0x7F800000, 0xFF800000, 0xFFC00000) - yield from check_case(dut, 0xFF800000, 0x7F800000, 0x7FC00000) yield from check_case(dut, 0x00018643, 0x00FA72A4, 0x00FBF8E7) yield from check_case(dut, 0x001A2239, 0x00FA72A4, 0x010A4A6E) yield from check_case(dut, 0x3F7FFFFE, 0x3F7FFFFE, 0x3FFFFFFE)