From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 30 Mar 2020 15:06:33 +0000 (+0100)
Subject: add signals for all fields, accessible by named tuples as fields
X-Git-Tag: div_pipeline~1600
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5374cb82b3e5d92bcc1ce1633ed93216067b8125;p=soc.git

add signals for all fields, accessible by named tuples as fields
---

diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py
index f349e6bb..a3d67fb1 100644
--- a/src/soc/decoder/power_decoder.py
+++ b/src/soc/decoder/power_decoder.py
@@ -53,6 +53,7 @@ Top Level:
 
 """
 
+from collections import namedtuple
 from nmigen import Module, Elaboratable, Signal, Cat, Mux
 from nmigen.cli import rtlil
 from soc.decoder.power_enums import (Function, Form, InternalOp,
@@ -239,7 +240,7 @@ class TopPowerDecoder(PowerDecoder):
 
     def __init__(self, width, dec):
         PowerDecoder.__init__(self, width, dec)
-        self.fields = DecodeFields(SignalBitRange, [self.opcode_in])
+        self.fields = df = DecodeFields(SignalBitRange, [self.opcode_in])
         self.fields.create_specs()
         self.raw_opcode_in = Signal.like(self.opcode_in, reset_less=True)
         self.bigendian = Signal(reset_less=True)
@@ -249,6 +250,7 @@ class TopPowerDecoder(PowerDecoder):
             sig = Signal(value[0:-1].shape(), reset_less=True, name=name)
             setattr(self, name, sig)
 
+
     def elaborate(self, platform):
         m = PowerDecoder.elaborate(self, platform)
         comb = m.d.comb
@@ -259,10 +261,30 @@ class TopPowerDecoder(PowerDecoder):
         l.reverse()
         raw_le = Cat(*l)
         comb += self.opcode_in.eq(Mux(self.bigendian, raw_be, raw_le))
+
+        # add all signal from commonly-used fields
         for name in self.fields.common_fields:
             value = getattr(self.fields, name)
             sig = getattr(self, name)
             comb += sig.eq(value[0:-1])
+
+        # create signals for all field forms
+        self.form_names = forms = self.fields.instrs.keys()
+        self.sigforms = {}
+        for form in forms:
+            fields = self.fields.instrs[form]
+            fk = fields.keys()
+            Fields = namedtuple("Fields", fk)
+            sf = {}
+            for k, value in fields.items():
+                name = "%s_%s" % (form, k)
+                sig = Signal(value[0:-1].shape(), reset_less=True, name=name)
+                sf[k] = sig
+                comb += sig.eq(value[0:-1])
+            instr = Fields(**sf)
+            setattr(self, "Form%s" % form, instr)
+            self.sigforms[form] = instr
+
         return m
 
     def ports(self):
diff --git a/src/soc/decoder/power_fields.py b/src/soc/decoder/power_fields.py
index cf0544d2..e0c01427 100644
--- a/src/soc/decoder/power_fields.py
+++ b/src/soc/decoder/power_fields.py
@@ -112,7 +112,7 @@ class DecodeFields:
     def create_specs(self):
         self.forms, self.instrs = self.decode_fields()
         self.form_names = forms = self.instrs.keys()
-        print ("specs", self.forms, forms)
+        #print ("specs", self.forms, forms)
         for form in forms:
             fields = self.instrs[form]
             fk = fields.keys()
@@ -163,7 +163,7 @@ class DecodeFields:
     def decode_fields(self):
         with open(self.fname) as f:
             txt = f.readlines()
-        print ("decode", txt)
+        #print ("decode", txt)
         forms = {}
         reading_data = False
         for l in txt: