From: klehman <klehman9@comcast.net>
Date: Thu, 9 Sep 2021 13:01:50 +0000 (-0400)
Subject: HDL int reg added
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53763d71664e428f8cacd792e58a0f8ecafb1909;p=soc.git

HDL int reg added
---

diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py
index 6266868d..ad361b40 100644
--- a/src/soc/simple/test/teststate.py
+++ b/src/soc/simple/test/teststate.py
@@ -1,5 +1,4 @@
 from openpower.decoder.power_enums import XER_bits
-import copy
 
 
 class SimState:
@@ -30,4 +29,17 @@ class SimState:
     def get_pc(self):
         self.pc = self.sim.pc.CIA.value
 
-# class HDLState:
+
+class HDLState:
+    def __init__(self, core):
+        self.core = core
+
+    def get_intregs(self):
+        self.intregs = []
+        for i in range(32):
+            if self.core.regs.int.unary:
+                rval = yield self.core.regs.int.regs[i].reg
+            else:
+                rval = yield self.core.regs.int.memory_array[i]
+            self.intregs.append(rval)
+        print("class core int regs", list(map(hex, intregs)))