From: Kristian H. Kristensen Date: Tue, 29 Oct 2019 23:26:34 +0000 (-0700) Subject: freedreno/a6xx: Only use merged regs and four quads for VS+FS X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53782571ae3b7c3f112c01914937ee622b6690c5;p=mesa.git freedreno/a6xx: Only use merged regs and four quads for VS+FS When other geometry stages are present, we chose two quads and no merged regs. Acked-by: Eric Anholt Signed-off-by: Kristian H. Kristensen Reviewed-by: Rob Clark --- diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c index 5e54c7ea6d5..213db91ff1c 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c @@ -410,13 +410,26 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen, A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) | 0xfc000000); + enum a3xx_threadsize vssz; + uint32_t vsregs; + if (ds || hs) { + vssz = TWO_QUADS; + vsregs = 0; + } else { + vssz = FOUR_QUADS; + vsregs = A6XX_SP_VS_CTRL_REG0_MERGEDREGS; + } + OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1); - OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz) | + OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(vssz) | A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) | - A6XX_SP_VS_CTRL_REG0_MERGEDREGS | + vsregs | A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack) | COND(vs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE)); + fd6_emit_shader(ring, vs); + ir3_emit_immediates(screen, vs, ring); + struct ir3_shader_linkage l = {0}; const struct ir3_shader_variant *last_shader = fd6_last_shader(state); ir3_link_shaders(&l, last_shader, fs); @@ -497,9 +510,6 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen, OUT_RING(ring, reg); } - fd6_emit_shader(ring, vs); - ir3_emit_immediates(screen, vs, ring); - if (hs) { OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1); OUT_RING(ring, A6XX_SP_HS_CTRL_REG0_THREADSIZE(TWO_QUADS) |