From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 9 Nov 2018 20:03:13 +0000 (+0100)
Subject: Set Verific flag vhdl_support_variable_slice=1
X-Git-Tag: yosys-0.9~411
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5387ccb041f4acafc96c7b3fcf8db04dddfb8ab5;p=yosys.git

Set Verific flag vhdl_support_variable_slice=1

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index dba3b0f0c..971f0b24a 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1835,6 +1835,7 @@ struct VerificPass : public Pass {
 			Message::RegisterCallBackMsg(msg_func);
 			RuntimeFlags::SetVar("db_preserve_user_nets", 1);
 			RuntimeFlags::SetVar("db_allow_external_nets", 1);
+			RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
 			RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
 			RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
 			RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);