From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 24 Jul 2019 08:28:55 +0000 (+0100)
Subject: add fsqrt test
X-Git-Tag: ls180-24jan2020~737
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5389ebd1ee0db611d65da23d70bf817fd009cf7c;p=ieee754fpu.git

add fsqrt test
---

diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py
index a01ea3c9..4d2a3b26 100644
--- a/src/ieee754/fpcommon/test/fpmux.py
+++ b/src/ieee754/fpcommon/test/fpmux.py
@@ -165,6 +165,12 @@ def create_random(num_rows, width, single_op=False, n_vals=10):
                 #op1 = 0x3449f9a9
                 #op1 = 0x1ba94baa
 
+                # FRSQRT
+                #op1 = 0x3686
+                #op1 = 0x4400
+                #op1 = 0x4800
+                #op1 = 0x48f0
+
                 vals.append((op1,))
             else:
                 op1 = randint(0, (1<<width)-1)
diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 91baea6b..d09e80e0 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -114,6 +114,21 @@ class FPDivStage0Mod(Elaboratable):
                              self.o.operation.eq(Const(1)) # XXX SQRT operation
                     ]
 
+            # RSQRT
+            with m.Elif(self.i.ctx.op == 2):
+                am0 = Signal(len(self.i.a.m)+3, reset_less=True)
+                with m.If(self.i.a.e[0]):
+                    m.d.comb += am0.eq(Cat(self.i.a.m, 0)<<(extra-2))
+                    m.d.comb += self.o.z.e.eq(-((self.i.a.e+1) >> 1)+1)
+                with m.Else():
+                    m.d.comb += am0.eq(Cat(0, self.i.a.m)<<(extra-2))
+                    m.d.comb += self.o.z.e.eq((self.i.a.e >> 1)+1)
+
+                m.d.comb += [self.o.z.s.eq(self.i.a.s),
+                             self.o.divisor_radicand.eq(am0),
+                             self.o.operation.eq(Const(2)) # XXX RSQRT operation
+                    ]
+
         # these are required and must not be touched
         m.d.comb += self.o.oz.eq(self.i.oz)
         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
diff --git a/src/ieee754/fpdiv/test/test_fprsqrt_pipe.py b/src/ieee754/fpdiv/test/test_fprsqrt_pipe.py
new file mode 100644
index 00000000..b196d3ea
--- /dev/null
+++ b/src/ieee754/fpdiv/test/test_fprsqrt_pipe.py
@@ -0,0 +1,30 @@
+""" test of FPDIVMuxInOut
+"""
+
+from ieee754.fpdiv.pipeline import (FPDIVMuxInOut,)
+from ieee754.fpcommon.test.fpmux import runfp
+
+from sfpy import Float64, Float32, Float16
+
+def rsqrt(x):
+    return x.__class__(1.0) / x.sqrt()
+
+def test_pipe_rsqrt_fp16():
+    dut = FPDIVMuxInOut(16, 4)
+    runfp(dut, 16, "test_fprsqrt_pipe_fp16", Float16, rsqrt,
+          single_op=True, opcode=2, n_vals=100)
+
+def test_pipe_rsqrt_fp32():
+    dut = FPDIVMuxInOut(32, 4)
+    runfp(dut, 32, "test_fprsqrt_pipe_fp32", Float32, rsqrt,
+          single_op=True, opcode=2, n_vals=100)
+
+def test_pipe_rsqrt_fp64():
+    dut = FPDIVMuxInOut(64, 4)
+    runfp(dut, 64, "test_fprsqrt_pipe_fp64", Float64, rsqrt,
+          single_op=True, opcode=2, n_vals=100)
+
+if __name__ == '__main__':
+    test_pipe_rsqrt_fp16()
+    test_pipe_rsqrt_fp32()
+    test_pipe_rsqrt_fp64()