From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Oct 2018 04:16:16 +0000 (+0000)
Subject: add sv_ld_elwidth test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53935fd33554002d91c55beb315564baea66fa13;p=riscv-tests.git

add sv_ld_elwidth test
---

diff --git a/isa/rv64ui/Makefrag.sv b/isa/rv64ui/Makefrag.sv
index 86b85fb..1d25de8 100644
--- a/isa/rv64ui/Makefrag.sv
+++ b/isa/rv64ui/Makefrag.sv
@@ -10,6 +10,7 @@ rv64ui_sv_tests = \
 	sv_addi_predicated \
 	sv_add_elwidth \
 	sv_addw_elwidth \
+	sv_ld_elwidth \
 	sv_beq \
 
 rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sv_tests))
diff --git a/isa/rv64ui/sv_ld_elwidth.S b/isa/rv64ui/sv_ld_elwidth.S
new file mode 100644
index 0000000..99ed4e3
--- /dev/null
+++ b/isa/rv64ui/sv_ld_elwidth.S
@@ -0,0 +1,76 @@
+#include "riscv_test.h"
+#include "sv_test_macros.h"
+
+RVTEST_RV64U        # Define TVM used by program.
+
+#define SV_ELWIDTH_TEST( inst, vl, elwidth, wid1, wid2, \
+                         testdata, expect1, expect2, expect3 ) \
+                                                        \
+        la x12, testdata ;                              \
+        la x13, (testdata+elwidth);                              \
+        la x14, (testdata+elwidth*2);                              \
+        la x15, (testdata+elwidth*3);                              \
+        la x16, (testdata+elwidth*4);                              \
+        la x17, (testdata+elwidth*5);                              \
+                                                        \
+        li x28, 0xa5a5a5a5a5a5a5a5;                                      \
+        li x29, 0xa5a5a5a5a5a5a5a5;                                      \
+        li x30, 0xa5a5a5a5a5a5a5a5;                                      \
+                                                        \
+        SET_SV_MVL( vl);                                  \
+        SET_SV_2CSRS( SV_REG_CSR( 1, 12, wid1, 12, 1),        \
+                      SV_REG_CSR( 1, 28, wid2, 28, 1));       \
+        SET_SV_VL( vl );                                   \
+                                                        \
+        inst   x28, 0(x12);                              \
+                                                        \
+        CLR_SV_CSRS();                                  \
+        SET_SV_VL( 1);                                   \
+        SET_SV_MVL( 1);                                  \
+                                                        \
+        TEST_SV_IMM( x28, expect1 );                         \
+        TEST_SV_IMM( x29, expect2 );                       \
+        TEST_SV_IMM( x30, expect3 );
+
+
+# SV test: vector-vector add
+#
+# sets up x3 and x4 with data, sets VL to 2, and carries out
+# an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
+
+# Test code region.
+RVTEST_CODE_BEGIN   # Start of test code.
+
+        SV_ELWIDTH_TEST(  ld , 2, 8, 0, 0, testdata1,
+                0x8979695949398979,  0x8777675747372717,  0xa5a5a5a5a5a5a5a5 )
+        SV_ELWIDTH_TEST(  ld , 3, 8, 0, 0, testdata1,
+                0x8979695949398979,  0x8777675747372717,  0x8676665646362616 )
+        SV_ELWIDTH_TEST(  ld , 3, 8, 2, 0, testdata1,
+                0xffffffffffff8979,  0x0000000000004939,  0x0000000000006959 )
+
+        RVTEST_PASS           # Signal success.
+fail:
+        RVTEST_FAIL
+RVTEST_CODE_END     # End of test code.
+
+# Input data section.
+# This section is optional, and this data is NOT saved in the output.
+.data
+        .align 3
+testdata1:
+        .dword 0x8979695949398979
+        .dword 0x8777675747372717
+        .dword 0x8676665646362616
+        .dword 0x8272625242322212
+        .dword 0x8171615141312111
+        .dword 0x8373635343332313
+
+# Output data section.
+RVTEST_DATA_BEGIN   # Start of test output data region.
+        .align 3
+result:
+        .dword -1
+        .dword -1
+        .dword -1
+RVTEST_DATA_END     # End of test output data region.
+