From: DJ Delorie Date: Tue, 14 Mar 2006 04:23:52 +0000 (+0000) Subject: * m32c-asm.c: Regenerate. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5398310abcbb731dab6708072b9e911ccd9dc1dd;p=binutils-gdb.git * m32c-asm.c: Regenerate. * m32c-desc.c: Likewise. * m32c-desc.h: Likewise. * m32c-dis.c: Likewise. * m32c-ibld.c: Likewise. * m32c-opc.c: Likewise. * m32c-opc.h: Likewise. --- diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b883ad4ccc0..863d128c5b5 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,6 +1,10 @@ 2006-03-13 DJ Delorie - * m32c-desc.c: Regenerate. + * m32c-asm.c: Regenerate. + * m32c-desc.c: Likewise. + * m32c-desc.h: Likewise. + * m32c-dis.c: Likewise. + * m32c-ibld.c: Likewise. * m32c-opc.c: Likewise. * m32c-opc.h: Likewise. diff --git a/opcodes/m32c-asm.c b/opcodes/m32c-asm.c index e2d8c490646..9407ed8d2d1 100644 --- a/opcodes/m32c-asm.c +++ b/opcodes/m32c-asm.c @@ -503,6 +503,24 @@ parse_imm3_S (CGEN_CPU_DESC cd, const char **strp, return 0; } +static const char * +parse_bit3_S (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value < 0 || value > 7) + return _("immediate is out of range 0-7"); + + *valuep = value; + return 0; +} + static const char * parse_lab_5_3 (CGEN_CPU_DESC cd, const char **strp, @@ -933,6 +951,9 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_BIT16RN : errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_dst16_rn); break; + case M32C_OPERAND_BIT3_S : + errmsg = parse_bit3_S (cd, strp, M32C_OPERAND_BIT3_S, (long *) (& fields->f_imm3_S)); + break; case M32C_OPERAND_BIT32ANPREFIXED : errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_prefixed); break; diff --git a/opcodes/m32c-desc.c b/opcodes/m32c-desc.c index 929a1cad15a..c87ddc7631e 100644 --- a/opcodes/m32c-desc.c +++ b/opcodes/m32c-desc.c @@ -1732,6 +1732,10 @@ const CGEN_OPERAND m32c_cgen_operand_table[] = { "Imm3-S", M32C_OPERAND_IMM3_S, HW_H_SINT, 2, 3, { 2, { (const PTR) &M32C_F_IMM3_S_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { { { (1<f_dst16_rn, 0); break; + case M32C_OPERAND_BIT3_S : + print_normal (cd, info, fields->f_imm3_S, 0|(1<f_dst32_an_prefixed, 0); break; diff --git a/opcodes/m32c-ibld.c b/opcodes/m32c-ibld.c index 7601128c634..31d5f9f99cf 100644 --- a/opcodes/m32c-ibld.c +++ b/opcodes/m32c-ibld.c @@ -578,6 +578,20 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_BIT16RN : errmsg = insert_normal (cd, fields->f_dst16_rn, 0, 0, 14, 2, 32, total_length, buffer); break; + case M32C_OPERAND_BIT3_S : + { +{ + FLD (f_7_1) = ((((FLD (f_imm3_S)) - (1))) & (1)); + FLD (f_2_2) = ((((unsigned int) (((FLD (f_imm3_S)) - (1))) >> (1))) & (3)); +} + errmsg = insert_normal (cd, fields->f_2_2, 0, 0, 2, 2, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_7_1, 0, 0, 7, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; case M32C_OPERAND_BIT32ANPREFIXED : errmsg = insert_normal (cd, fields->f_dst32_an_prefixed, 0, 0, 17, 1, 32, total_length, buffer); break; @@ -1738,6 +1752,17 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_BIT16RN : length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 2, 32, total_length, pc, & fields->f_dst16_rn); break; + case M32C_OPERAND_BIT3_S : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 2, 32, total_length, pc, & fields->f_2_2); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_7_1); + if (length <= 0) break; +{ + FLD (f_imm3_S) = ((((((FLD (f_2_2)) << (1))) | (FLD (f_7_1)))) + (1)); +} + } + break; case M32C_OPERAND_BIT32ANPREFIXED : length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_dst32_an_prefixed); break; @@ -2861,6 +2886,9 @@ m32c_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_BIT16RN : value = fields->f_dst16_rn; break; + case M32C_OPERAND_BIT3_S : + value = fields->f_imm3_S; + break; case M32C_OPERAND_BIT32ANPREFIXED : value = fields->f_dst32_an_prefixed; break; @@ -3451,6 +3479,9 @@ m32c_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_BIT16RN : value = fields->f_dst16_rn; break; + case M32C_OPERAND_BIT3_S : + value = fields->f_imm3_S; + break; case M32C_OPERAND_BIT32ANPREFIXED : value = fields->f_dst32_an_prefixed; break; @@ -4046,6 +4077,9 @@ m32c_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_BIT16RN : fields->f_dst16_rn = value; break; + case M32C_OPERAND_BIT3_S : + fields->f_imm3_S = value; + break; case M32C_OPERAND_BIT32ANPREFIXED : fields->f_dst32_an_prefixed = value; break; @@ -4614,6 +4648,9 @@ m32c_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_BIT16RN : fields->f_dst16_rn = value; break; + case M32C_OPERAND_BIT3_S : + fields->f_imm3_S = value; + break; case M32C_OPERAND_BIT32ANPREFIXED : fields->f_dst32_an_prefixed = value; break; diff --git a/opcodes/m32c-opc.c b/opcodes/m32c-opc.c index 66d99b0fa7e..2d051cbc4dd 100644 --- a/opcodes/m32c-opc.c +++ b/opcodes/m32c-opc.c @@ -7709,6 +7709,10 @@ static const CGEN_IFMT ifmt_brk16 ATTRIBUTE_UNUSED = { 8, 8, 0xff, { { F (F_0_4) }, { F (F_4_4) }, { 0 } } }; +static const CGEN_IFMT ifmt_btst_s ATTRIBUTE_UNUSED = { + 24, 24, 0xce0000, { { F (F_0_2) }, { F (F_IMM3_S) }, { F (F_4_3) }, { F (F_DSP_8_U16) }, { 0 } } +}; + static const CGEN_IFMT ifmt_dec16_w ATTRIBUTE_UNUSED = { 8, 8, 0xf7, { { F (F_0_4) }, { F (F_DST16_AN_S) }, { F (F_5_3) }, { 0 } } }; @@ -79202,6 +79206,12 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, 0 } }, & ifmt_brk16, { 0x8 } }, +/* btst:s ${Bit3-S},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (BIT3_S), ',', OP (DSP_8_U16), 0 } }, + & ifmt_btst_s, { 0xa0000 } + }, /* dec.w ${Dst16An-S} */ { { 0, 0, 0, 0 }, diff --git a/opcodes/m32c-opc.h b/opcodes/m32c-opc.h index 8efaf5186f3..7f0e6e566dc 100644 --- a/opcodes/m32c-opc.h +++ b/opcodes/m32c-opc.h @@ -3018,41 +3018,42 @@ typedef enum cgen_insn_type { , M32C_INSN_DADC16_W_IMM16, M32C_INSN_DADC16_B_R0H_R0L, M32C_INSN_DADC16_W_R1_R0, M32C_INSN_DADD16_B_IMM8 , M32C_INSN_DADD16_W_IMM16, M32C_INSN_DADD16_B_R0H_R0L, M32C_INSN_DADD16_W_R1_R0, M32C_INSN_BM16_C , M32C_INSN_BM32_C, M32C_INSN_BRK16, M32C_INSN_BRK32, M32C_INSN_BRK232 - , M32C_INSN_DEC16_W, M32C_INSN_DIV16_B_IMM_16_QI, M32C_INSN_DIV16_W_IMM_16_HI, M32C_INSN_DIV32_B_IMM_16_QI - , M32C_INSN_DIV32_W_IMM_16_HI, M32C_INSN_DIVU16_B_IMM_16_QI, M32C_INSN_DIVU16_W_IMM_16_HI, M32C_INSN_DIVU32_B_IMM_16_QI - , M32C_INSN_DIVU32_W_IMM_16_HI, M32C_INSN_DIVX16_B_IMM_16_QI, M32C_INSN_DIVX16_W_IMM_16_HI, M32C_INSN_DIVX32_B_IMM_16_QI - , M32C_INSN_DIVX32_W_IMM_16_HI, M32C_INSN_DSBB16_B_IMM8, M32C_INSN_DSBB16_W_IMM16, M32C_INSN_DSBB16_B_R0H_R0L - , M32C_INSN_DSBB16_W_R1_R0, M32C_INSN_DSUB16_B_IMM8, M32C_INSN_DSUB16_W_IMM16, M32C_INSN_DSUB16_B_R0H_R0L - , M32C_INSN_DSUB16_W_R1_R0, M32C_INSN_ENTER16, M32C_INSN_EXITD16, M32C_INSN_ENTER32 - , M32C_INSN_EXITD32, M32C_INSN_FCLR16, M32C_INSN_FSET16, M32C_INSN_FCLR - , M32C_INSN_FSET, M32C_INSN_INC16_W, M32C_INSN_FREIT32, M32C_INSN_INT16 - , M32C_INSN_INTO16, M32C_INSN_INT32, M32C_INSN_INTO32, M32C_INSN_JCND16_5 - , M32C_INSN_JCND16, M32C_INSN_JCND32, M32C_INSN_JMP16_S, M32C_INSN_JMP16_B - , M32C_INSN_JMP16_W, M32C_INSN_JMP16_A, M32C_INSN_JMPS16, M32C_INSN_JMP32_S - , M32C_INSN_JMP32_B, M32C_INSN_JMP32_W, M32C_INSN_JMP32_A, M32C_INSN_JMPS32 - , M32C_INSN_JSR16_W, M32C_INSN_JSR16_A, M32C_INSN_JSR32_W, M32C_INSN_JSR32_A - , M32C_INSN_JSRS16, M32C_INSN_JSRS, M32C_INSN_LDC16_IMM16, M32C_INSN_LDC32_IMM16_CR1 - , M32C_INSN_LDC32_IMM16_CR2, M32C_INSN_LDC32_IMM16_CR3, M32C_INSN_LDCTX16, M32C_INSN_LDCTX32 - , M32C_INSN_STCTX16, M32C_INSN_STCTX32, M32C_INSN_LDIPL16_IMM, M32C_INSN_LDIPL32_IMM - , M32C_INSN_MOV16_B_S_IMM_A0, M32C_INSN_MOV16_B_S_IMM_A1, M32C_INSN_MOV16_W_S_IMM_A0, M32C_INSN_MOV16_W_S_IMM_A1 - , M32C_INSN_MOV32_W_A0, M32C_INSN_MOV32_W_A1, M32C_INSN_MOV32_L_A0, M32C_INSN_MOV32_L_A1 - , M32C_INSN_MOV16_B_S_R0L_A1, M32C_INSN_MOV16_B_S_R0H_A0, M32C_INSN_NOP16, M32C_INSN_NOP32 - , M32C_INSN_POPC16_IMM16, M32C_INSN_POPC32_IMM16_CR1, M32C_INSN_POPC32_IMM16_CR2, M32C_INSN_PUSHC16_IMM16 - , M32C_INSN_PUSHC32_IMM16_CR1, M32C_INSN_PUSHC32_IMM16_CR2, M32C_INSN_POPM16, M32C_INSN_PUSHM16 - , M32C_INSN_POPM, M32C_INSN_PUSHM, M32C_INSN_PUSH16_B_G_IMM, M32C_INSN_PUSH16_W_G_IMM - , M32C_INSN_PUSH32_B_IMM, M32C_INSN_PUSH32_W_IMM, M32C_INSN_PUSH32_L_IMM, M32C_INSN_REIT16 - , M32C_INSN_REIT32, M32C_INSN_RMPA16_B, M32C_INSN_RMPA16_W, M32C_INSN_RMPA32_B - , M32C_INSN_RMPA32_W, M32C_INSN_RTS16, M32C_INSN_RTS32, M32C_INSN_SCMPU_B - , M32C_INSN_SCMPU_W, M32C_INSN_SHA16_L_IMM_R2R0, M32C_INSN_SHA16_L_IMM_R3R1, M32C_INSN_SHA16_L_R1H_R2R0 - , M32C_INSN_SHA16_L_R1H_R3R1, M32C_INSN_SHL16_L_IMM_R2R0, M32C_INSN_SHL16_L_IMM_R3R1, M32C_INSN_SHL16_L_R1H_R2R0 - , M32C_INSN_SHL16_L_R1H_R3R1, M32C_INSN_SIN32_B, M32C_INSN_SIN32_W, M32C_INSN_SMOVB16_B - , M32C_INSN_SMOVB16_W, M32C_INSN_SMOVB32_B, M32C_INSN_SMOVB32_W, M32C_INSN_SMOVF16_B - , M32C_INSN_SMOVF16_W, M32C_INSN_SMOVF32_B, M32C_INSN_SMOVF32_W, M32C_INSN_SMOVU_B - , M32C_INSN_SMOVU_W, M32C_INSN_SOUT_B, M32C_INSN_SOUT_W, M32C_INSN_SSTR16_B - , M32C_INSN_SSTR16_W, M32C_INSN_SSTR_B, M32C_INSN_SSTR_W, M32C_INSN_STZX16_IMM8_IMM8_R0H - , M32C_INSN_STZX16_IMM8_IMM8_R0L, M32C_INSN_STZX16_IMM8_IMM8_DSP8SB, M32C_INSN_STZX16_IMM8_IMM8_DSP8FB, M32C_INSN_STZX16_IMM8_IMM8_ABS16 - , M32C_INSN_UND16, M32C_INSN_UND32, M32C_INSN_WAIT16, M32C_INSN_WAIT - , M32C_INSN_EXTS16_W_R0, M32C_INSN_SRCIND, M32C_INSN_DESTIND, M32C_INSN_SRCDESTIND + , M32C_INSN_BTST_S, M32C_INSN_DEC16_W, M32C_INSN_DIV16_B_IMM_16_QI, M32C_INSN_DIV16_W_IMM_16_HI + , M32C_INSN_DIV32_B_IMM_16_QI, M32C_INSN_DIV32_W_IMM_16_HI, M32C_INSN_DIVU16_B_IMM_16_QI, M32C_INSN_DIVU16_W_IMM_16_HI + , M32C_INSN_DIVU32_B_IMM_16_QI, M32C_INSN_DIVU32_W_IMM_16_HI, M32C_INSN_DIVX16_B_IMM_16_QI, M32C_INSN_DIVX16_W_IMM_16_HI + , M32C_INSN_DIVX32_B_IMM_16_QI, M32C_INSN_DIVX32_W_IMM_16_HI, M32C_INSN_DSBB16_B_IMM8, M32C_INSN_DSBB16_W_IMM16 + , M32C_INSN_DSBB16_B_R0H_R0L, M32C_INSN_DSBB16_W_R1_R0, M32C_INSN_DSUB16_B_IMM8, M32C_INSN_DSUB16_W_IMM16 + , M32C_INSN_DSUB16_B_R0H_R0L, M32C_INSN_DSUB16_W_R1_R0, M32C_INSN_ENTER16, M32C_INSN_EXITD16 + , M32C_INSN_ENTER32, M32C_INSN_EXITD32, M32C_INSN_FCLR16, M32C_INSN_FSET16 + , M32C_INSN_FCLR, M32C_INSN_FSET, M32C_INSN_INC16_W, M32C_INSN_FREIT32 + , M32C_INSN_INT16, M32C_INSN_INTO16, M32C_INSN_INT32, M32C_INSN_INTO32 + , M32C_INSN_JCND16_5, M32C_INSN_JCND16, M32C_INSN_JCND32, M32C_INSN_JMP16_S + , M32C_INSN_JMP16_B, M32C_INSN_JMP16_W, M32C_INSN_JMP16_A, M32C_INSN_JMPS16 + , M32C_INSN_JMP32_S, M32C_INSN_JMP32_B, M32C_INSN_JMP32_W, M32C_INSN_JMP32_A + , M32C_INSN_JMPS32, M32C_INSN_JSR16_W, M32C_INSN_JSR16_A, M32C_INSN_JSR32_W + , M32C_INSN_JSR32_A, M32C_INSN_JSRS16, M32C_INSN_JSRS, M32C_INSN_LDC16_IMM16 + , M32C_INSN_LDC32_IMM16_CR1, M32C_INSN_LDC32_IMM16_CR2, M32C_INSN_LDC32_IMM16_CR3, M32C_INSN_LDCTX16 + , M32C_INSN_LDCTX32, M32C_INSN_STCTX16, M32C_INSN_STCTX32, M32C_INSN_LDIPL16_IMM + , M32C_INSN_LDIPL32_IMM, M32C_INSN_MOV16_B_S_IMM_A0, M32C_INSN_MOV16_B_S_IMM_A1, M32C_INSN_MOV16_W_S_IMM_A0 + , M32C_INSN_MOV16_W_S_IMM_A1, M32C_INSN_MOV32_W_A0, M32C_INSN_MOV32_W_A1, M32C_INSN_MOV32_L_A0 + , M32C_INSN_MOV32_L_A1, M32C_INSN_MOV16_B_S_R0L_A1, M32C_INSN_MOV16_B_S_R0H_A0, M32C_INSN_NOP16 + , M32C_INSN_NOP32, M32C_INSN_POPC16_IMM16, M32C_INSN_POPC32_IMM16_CR1, M32C_INSN_POPC32_IMM16_CR2 + , M32C_INSN_PUSHC16_IMM16, M32C_INSN_PUSHC32_IMM16_CR1, M32C_INSN_PUSHC32_IMM16_CR2, M32C_INSN_POPM16 + , M32C_INSN_PUSHM16, M32C_INSN_POPM, M32C_INSN_PUSHM, M32C_INSN_PUSH16_B_G_IMM + , M32C_INSN_PUSH16_W_G_IMM, M32C_INSN_PUSH32_B_IMM, M32C_INSN_PUSH32_W_IMM, M32C_INSN_PUSH32_L_IMM + , M32C_INSN_REIT16, M32C_INSN_REIT32, M32C_INSN_RMPA16_B, M32C_INSN_RMPA16_W + , M32C_INSN_RMPA32_B, M32C_INSN_RMPA32_W, M32C_INSN_RTS16, M32C_INSN_RTS32 + , M32C_INSN_SCMPU_B, M32C_INSN_SCMPU_W, M32C_INSN_SHA16_L_IMM_R2R0, M32C_INSN_SHA16_L_IMM_R3R1 + , M32C_INSN_SHA16_L_R1H_R2R0, M32C_INSN_SHA16_L_R1H_R3R1, M32C_INSN_SHL16_L_IMM_R2R0, M32C_INSN_SHL16_L_IMM_R3R1 + , M32C_INSN_SHL16_L_R1H_R2R0, M32C_INSN_SHL16_L_R1H_R3R1, M32C_INSN_SIN32_B, M32C_INSN_SIN32_W + , M32C_INSN_SMOVB16_B, M32C_INSN_SMOVB16_W, M32C_INSN_SMOVB32_B, M32C_INSN_SMOVB32_W + , M32C_INSN_SMOVF16_B, M32C_INSN_SMOVF16_W, M32C_INSN_SMOVF32_B, M32C_INSN_SMOVF32_W + , M32C_INSN_SMOVU_B, M32C_INSN_SMOVU_W, M32C_INSN_SOUT_B, M32C_INSN_SOUT_W + , M32C_INSN_SSTR16_B, M32C_INSN_SSTR16_W, M32C_INSN_SSTR_B, M32C_INSN_SSTR_W + , M32C_INSN_STZX16_IMM8_IMM8_R0H, M32C_INSN_STZX16_IMM8_IMM8_R0L, M32C_INSN_STZX16_IMM8_IMM8_DSP8SB, M32C_INSN_STZX16_IMM8_IMM8_DSP8FB + , M32C_INSN_STZX16_IMM8_IMM8_ABS16, M32C_INSN_UND16, M32C_INSN_UND32, M32C_INSN_WAIT16 + , M32C_INSN_WAIT, M32C_INSN_EXTS16_W_R0, M32C_INSN_SRCIND, M32C_INSN_DESTIND + , M32C_INSN_SRCDESTIND } CGEN_INSN_TYPE; /* Index of `invalid' insn place holder. */