From: Luke Kenneth Casson Leighton Date: Thu, 1 Oct 2020 20:38:04 +0000 (+0100) Subject: add litex-coriolis2 pad map X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53a0fdcfa1c8073b7d0e227c5cb14b1d9d87dd49;p=pinmux.git add litex-coriolis2 pad map --- diff --git a/src/pinmux_generator.py b/src/pinmux_generator.py index b95377b..4ceeec6 100644 --- a/src/pinmux_generator.py +++ b/src/pinmux_generator.py @@ -86,12 +86,13 @@ if __name__ == '__main__': os.makedirs(d) with open(fname, "w") as of: ps = module.pinspec() - pinout, bankspec, pinspec, fixedpins = ps.write(of) + pinout, bankspec, pin_spec, fixedpins = ps.write(of) if testing: dummytest(ps, output_dir, output_type) else: specgen(of, output_dir, pinout, - bankspec, ps.muxwidths, pinspec, fixedpins, ps.fastbus) + bankspec, ps.muxwidths, pin_spec, fixedpins, ps.fastbus) + module.pinparse(pinspec) else: if output_type == 'bsv': from bsv.pinmux_generator import pinmuxgen as gentypes diff --git a/src/spec/ls180.py b/src/spec/ls180.py index 3a795c8..7bd651b 100644 --- a/src/spec/ls180.py +++ b/src/spec/ls180.py @@ -2,6 +2,8 @@ # see https://bugs.libre-soc.org/show_bug.cgi?id=304 from spec.base import PinSpec +from parse import Parse +import json from spec.ifaceprint import display, display_fns, check_functions from spec.ifaceprint import display_fixed @@ -125,3 +127,200 @@ def pinspec(): descriptions) return ps + + +# map pins to litex name conventions, primarily for use in coriolis2 +def pinparse(pinspec): + p = Parse(pinspec, verify=False) + + print p.muxed_cells + print p.muxed_cells_bank + + ps = [''] * 32 + pn = [''] * 32 + pe = [''] * 32 + pw = [''] * 32 + pads = {'N': pn, 'S': ps, 'E': pe, 'W': pw} + + iopads = [] + + for (padnum, name, _), bank in zip(p.muxed_cells, p.muxed_cells_bank): + padnum = int(padnum) + start = p.bankstart[bank] + banknum = padnum - start + print banknum, name, bank + padbank = pads[bank] + # VSS + if name.startswith('vss'): + #name = 'p_vssick_' + name[-1] + #name = 'p_vsseck_0' + #name = 'vss' + name = '' + # VDD + elif name.startswith('vdd'): + #name = 'p_vddick_' + name[-1] + #name = 'p_vddeck_0' + #name = 'vdd' + name = '' + # SYS + elif name.startswith('sys'): + if name == 'sys_clk': + name = 'p_sys_clk_0' + elif name == 'sys_rst': + #name = 'p_sys_rst_1' + iopads.append([name, name, name]) + padbank[banknum] = name + print "sys_rst add", bank, banknum, name + name = None + elif name == 'sys_pllclk': + name = None # ignore + elif name == 'sys_pllout': + name = 'sys_pll_48_o' + iopads.append(['p_' + name, name, name]) + elif name.startswith('sys_csel'): + i = name[-1] + name2 = 'sys_clksel_i(%s)' % i + name = 'p_sys_clksel_' + i + iopads.append([name, name2, name2]) + #if name: + # iopads.append([pname, name, name]) + print "sys pad", name + # SPI Card + elif name.startswith('mspi0') or name.startswith('mspi1'): + suffix = name[6:] + if suffix == 'ck': + suffix = 'clk' + elif suffix == 'nss': + suffix = 'cs_n' + if name.startswith('mspi1'): + prefix = 'spi_master_' + else: + prefix = 'spisdcard_' + name = prefix + suffix + iopads.append(['p_' + name, name, name]) + # SD/MMC + elif name.startswith('sd0'): + if name.startswith('sd0_d'): + i = name[5:] + name = 'sdcard_data' + i + name2 = 'sdcard_data_%%s(%s)' % i + pad = ['p_' + name, name, name2 % 'o', name2 % 'i', + 'sdcard_data_oe'] + iopads.append(pad) + elif name.startswith('sd0_cmd'): + name = 'sdcard_cmd' + name2 = 'sdcard_cmd_%s' + pad = ['p_' + name, name, name2 % 'o', name2 % 'i', name2 % 'oe'] + iopads.append(pad) + else: + name = 'sdcard_' + name[4:] + iopads.append(['p_' + name, name, name]) + # SDRAM + elif name.startswith('sdr'): + if name == 'sdr_clk': + name = 'sdram_clock' + iopads.append(['p_' + name, name, name]) + elif name.startswith('sdr_ad'): + i = name[6:] + name = 'sdram_a_' + i + name2 = 'sdram_a(%s)' % i + iopads.append(['p_' + name, name2, name2]) + elif name.startswith('sdr_ba'): + i = name[-1] + name = 'sdram_ba_' + i + name2 = 'sdram_ba(%s)' % i + iopads.append(['p_' + name, name2, name2]) + elif name.startswith('sdr_dqm'): + i = name[-1] + name = 'sdram_dm_' + i + name2 = 'sdram_dm(%s)' % i + iopads.append(['p_' + name, name2, name2]) + elif name.startswith('sdr_d'): + i = name[5:] + name = 'sdram_dq_' + i + name2 = 'sdram_dq_%%s(%s)' % i + pad = ['p_' + name, name, name2 % 'o', name2 % 'i', 'sdram_dq_oe'] + iopads.append(pad) + elif name == 'sdr_csn0': + name = 'sdram_cs_n' + iopads.append(['p_' + name, name, name]) + elif name[-1] == 'n': + name = 'sdram_' + name[4:-1] + '_n' + iopads.append(['p_' + name, name, name]) + else: + name = 'sdram_' + name[4:] + iopads.append(['p_' + name, name, name]) + # UART + elif name.startswith('uart'): + name = 'uart_' + name[6:] + iopads.append(['p_' + name, name, name]) + # GPIO + elif name.startswith('gpio'): + i = name[7:] + name = 'gpio_' + i + name2 = 'gpio_%%s(%s)' % i + pad = ['p_' + name, name, name2 % 'o', name2 % 'i', name2 % 'oe'] + print ("GPIO pad", name, pad) + iopads.append(pad) + # I2C + elif name.startswith('twi'): + name = 'i2c' + name[3:] + if name.startswith('i2c_sda'): + name2 = 'i2c_sda_%s' + pad = ['p_' + name, name, name2 % 'o', name2 % 'i', name2 % 'oe'] + print ("I2C pad", name, pad) + iopads.append(pad) + else: + iopads.append(['p_' + name, name, name]) + # EINT + elif name.startswith('eint'): + i = name[-1] + name = 'eint_%s' % i + name2 = 'eint(%s)' % i + pad = ['p_' + name, name2, name2] + iopads.append(pad) + # PWM + elif name.startswith('pwm'): + name = name[:-4] + pad = ['p_' + name, name, name] + iopads.append(pad) + else: + pad = ['p_' + name, name, name] + iopads.append(pad) + print ("GPIO pad", name, pad) + if name and not name.startswith('p_'): + name = 'p_' + name + if name is not None: + padbank[banknum] = name + + #pw[25] = 'p_sys_rst_1' + pe[13] = 'p_vddeck_0' + pe[23] = 'p_vsseck_0' + pw[10] = 'p_vddick_0' + pw[17] = 'p_vssick_0' + + nc_idx = 0 + for pl in [pe, pw, pn, ps]: + for i in range(len(pl)): + if pl[i] == '': + pl[i] = 'nc_%d' % nc_idx + nc_idx += 1 + + print p.bankstart + print pn + print ps + print pe + print pw + + chip = { + 'pads.south' : ps, + 'pads.east' : pe, + 'pads.north' : pn, + 'pads.west' : pw, + 'pads.instances' : iopads + } + + chip = json.dumps(chip) + with open("ls180/litex_pinpads.json", "w") as f: + f.write(chip) +