From: bunnie <bunnie@kosagi.com>
Date: Sat, 18 Jul 2020 19:00:25 +0000 (+0800)
Subject: wire up missing register bits.
X-Git-Tag: 24jan2021_ls180~72^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53a567daef000f2d2457375bf610239c442fbec1;p=litex.git

wire up missing register bits.

Not sure how they went missing...but just noticed them.
---

diff --git a/litex/soc/cores/i2s.py b/litex/soc/cores/i2s.py
index a5dde4ca..78435683 100644
--- a/litex/soc/cores/i2s.py
+++ b/litex/soc/cores/i2s.py
@@ -283,10 +283,12 @@ class S7I2S(Module, AutoCSR, AutoDoc):
                 o_WRERR       = rx_wrerr,
             )
             self.comb += [  # Wire up the status signals and interrupts
+                self.rx_stat.fields.overflow.eq(rx_wrerr),
                 self.rx_stat.fields.underflow.eq(rx_rderr),
                 self.rx_stat.fields.dataready.eq(rx_almostfull),
                 self.rx_stat.fields.wrcount.eq(rx_wrcount),
                 self.rx_stat.fields.rdcount.eq(rx_rdcount),
+                self.rx_stat.fields.empty.eq(rx_empty),
                 self.ev.rx_ready.trigger.eq(rx_almostfull),
                 self.ev.rx_error.trigger.eq(rx_wrerr | rx_rderr),
             ]