From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 7 Jan 2020 00:21:04 +0000 (-0800)
Subject: Re-enable &mfs for synth_{ecp5,xilinx}
X-Git-Tag: working-ls180~873^2~9
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53aa51dc923467bf7aed46e646640e7cee7b009d;p=yosys.git

Re-enable &mfs for synth_{ecp5,xilinx}
---

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index d616391b2..6583f43fd 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -323,9 +323,9 @@ struct SynthEcp5Pass : public ScriptPass
 			if (abc9) {
 				run("read_verilog -icells -lib +/ecp5/abc9_model.v");
 				if (nowidelut)
-					run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
+					run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200");
 				else
-					run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
+					run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200");
 				run("techmap -map +/ecp5/abc9_unmap.v");
 			} else {
 				if (nowidelut)
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b0c4795ee..e1748562e 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -541,7 +541,6 @@ struct SynthXilinxPass : public ScriptPass
 				run("read_verilog -icells -lib +/xilinx/abc9_model.v");
 				std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
 				abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
-				abc9_opts += " -nomfs";
 				if (nowidelut)
 					abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
 				else