From: lkcl <lkcl@web>
Date: Sun, 30 Jun 2019 10:34:01 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4320
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53b90e44e278dc5f624a24a92ebe1f145dbd6a61;p=libreriscv.git

---

diff --git a/simple_v_extension/sv_prefix_proposal/discussion.rst b/simple_v_extension/sv_prefix_proposal/discussion.rst
index 3aca9d894..0bbb5f8a2 100644
--- a/simple_v_extension/sv_prefix_proposal/discussion.rst
+++ b/simple_v_extension/sv_prefix_proposal/discussion.rst
@@ -34,21 +34,12 @@ Or, just "to hell with it" and just take the entire opcode and stuff C into it,
 |funct3    |                jump target                       | op    | CJ     |
 +----------+--------------------------------------------------+-------+--------+
 
-* 16 bits RVC to go into RV128 "MAJOR OPCODE 2" and "MAJOR OPCODE 3".
-  RVC op[1:0], bit[1] selects OPCODE-2 or OPCODE-3, therefore
-  17 bits remain in the 32-bit opcode space
-* 32-bit opcode prefix takes 7 bits, therefore 10 bits remain to fit
+* top 14 bits of RVC to go into "MAJOR OPCODE 0-2" to represent
+  RVC op[1:0] == 0b00, 0b01 and 0b02.  Therefore,
+  18 bits remain in the 32-bit opcode space
+* 32-bit opcode prefix takes 7 bits, therefore 11 bits remain to fit
   a SVPrefix.
-* compared to P48, 11 bits are needed.
-* however, with the exception of LD/ST (and C.MV) these all provide *three*
-  operands: rs1, rs2 and rs3.
-* therefore, 1 field can go, and that just leaves what to do with LD/ST
-  and C.MV
-* should twin-predication be sacrificed?
-* should one of the vectorisation modes be sacrificed?
-* is there room in ohe of the other "MAJOR CUSTOM OPCODEs" (0,1) to
-  fit the "other" mode somehow?
-* can one of the vew bits be sacrificed instead, reducing vitp7 by 1 bit?
+* compared to P48, 11 bits are needed, and we have a match.
 
 P48:
 
@@ -74,23 +65,23 @@ P48:
 
 P32C:
 
-+---------------+--------+--------+----------+--------+-------------+------+--------+--------+
-| Encoding      | 17     | 16     | 15       | 13     | 12          | 11:7 | 6      | 5:0    |
-+---------------+--------+--------+----------+--------+-------------+------+--------+--------+
-| P32C-CL-type  | rd[5]  | rs1[5] | vitp7[6] | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
-+---------------+--------+--------+----------+--------+--------------------+--------+--------+
-| P32C-CS-type  |vitp7[6]| rs1[5] | rs2[5]   | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
-+---------------+--------+--------+----------+--------+-------------+------+--------+--------+
-| P32C-FR-type  | rd[5]  | rs1[5] | rs2[5]   | vs1    | *Rsvd*      | vtp5 | *Rsvd* | 011111 |
-+---------------+--------+--------+----------+--------+-------------+------+--------+--------+
-| P32C-FR-type  | rd[5]  | rs1[5] | rs2[5]   | vs1    | *Rsvd*      | vtp5 | *Rsvd* | 011111 |
-+---------------+--------+--------+----------+--------+-------------+------+--------+--------+
-| P32C-CR-type  | rd[5]  | rs1[5] | rs2[5]   | vs1    | vitp6              | *Rsvd* | 011111 |
-+---------------+--------+--------+----------+--------+--------------------+--------+--------+
-| P32C-CA-type  | rd[5]  | rs1[5] | vitp7[6] | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
-+---------------+--------+--------+----------+--------+--------------------+--------+--------+
-| P32C-CU-type  | rd[5]  | *Rsvd* | *Rsvd*   | *Rsvd* | vitp6              | *Rsvd* | 011111 |
-+---------------+--------+--------+----------+--------+--------------------+--------+--------+
+P48:
+
++---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
+| Encoding      | 17     | 16     | 15       | 14  | 13     | 12          | 11:7 | 6      | 5:0    |
++---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
+| P32C-CL-type  | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
++---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
+| P32C-CS-type  |vitp7[6]| rs1[5] | rs2[5]   | vs2 | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
++---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
+| P32C-CR-type  | rd[5]  | rs1[5] | *Rsvd*   | vd  | vs1    | vitp6              | *Rsvd* | 011111 |
++---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
+| P32C-CI1-type | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
++---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
+| P32C-CI2-type | rd[5]  | *Rsvd* | *Rsvd*   | vd  | *Rsvd* | vitp6              | *Rsvd* | 011111 |
++---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
+| P32C-CMv-type | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
++---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
 
 Questions
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