From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 06:27:49 +0000 (+0200)
Subject: Clean verilog code from not used define block
X-Git-Tag: working-ls180~990^2~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53bc499a907cc3bfbeb91866d8839286ae0dfdf1;p=yosys.git

Clean verilog code from not used define block
---

diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v
index c55632552..04ae49d83 100644
--- a/tests/xilinx/shifter.v
+++ b/tests/xilinx/shifter.v
@@ -9,14 +9,8 @@ in
 
     always @(posedge clk)
 	begin
-`ifndef BUG
 		out    <= out >> 1;
 		out[7] <= in;
-`else
-
-		out    <= out << 1;
-		out[7] <= in;
-`endif
 	end
 
 endmodule
diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v
index 3fa6eb6c6..75149d8ba 100644
--- a/tests/xilinx/tribuf.v
+++ b/tests/xilinx/tribuf.v
@@ -2,15 +2,9 @@ module tristate (en, i, o);
     input en;
     input i;
     output reg o;
-`ifndef BUG 
     
     always @(en or i)
 		o <= (en)? i : 1'bZ;
-`else
-	
-    always @(en or i)
-		o <= (en)? ~i : 1'bZ;
-`endif
 endmodule