From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 29 Jul 2022 12:05:26 +0000 (+0100)
Subject: clarify MyISA 66000g
X-Git-Tag: opf_rfc_ls005_v1~947
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53c3197a41494c221a61c7623e33f7acd052fea0;p=libreriscv.git

clarify MyISA 66000g
---

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index dc32db6cf..058930ebe 100644
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -9,7 +9,7 @@
 |AVX512 [^18]   |~1000s [^19]  |7256 [^30]       |Predicated SIMD     |no                 |yes                 |no           |yes             |see [^35]        |no      |no              |no                     |no              |yes [^34]    | no           |
 |RVV [^20]      |~190 [^21]    |~25000[^31]      |Scalable[^22]       |yes                |yes                 |no           |yes             |yes [^23]        |no      |yes             |no                     |no              |no           | no           |
 |Aurora SX[^24] |~200 [^25]    |unknown [^32]    |Scalable [^26]      |yes                |yes                 |no           |yes             |no               |no      |no              |no                     |no              |?            | no           |
-|66000[^36]     |~200          |unknown          |AutoVec[^36]        |see [^36]          |no [^36]            |no           |see [^36]       |no               |yes[^37]|see [^36]       |no                     |no              |no           | no           |
+|66000[^36]     |~200          |unknown          |AutoVec[^36]        |see [^36]          |see[^36]            |no           |see [^36]       |no               |yes[^37]|see [^36]       |no                     |no              |no           | no           |
 
 [^1]: plus EXT001 24-bit prefixing using 25% of EXT001 space. See [[sv/svp64]]
 [^3]: A 2-Dimensional Scalable Vector ISA **specifically designed for the Power ISA** with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]]
@@ -55,5 +55,5 @@
     which is very hard to tell at a glance if it is power-2 or non-power-2
 [^34]: [Advanced matrix Extensions](https://en.wikipedia.org/wiki/Advanced_Matrix_Extensions) supports BF16 and INT8 only. Separate regfile, power-of-two "tiles". Not general-purpose at all.
 [^35]: Although registers may be 128-bit in NEON, SVE2, and AVX, unlike VSX there are very few (or no) actual arithmetic 128-bit operations. Only RVV and SVP64 have the possibility of 128-bit ops 
-[^36]: Mitch Alsup's MyISA 66000 is available on request. An extremely powerful RISC ISA with an auto-vectorisation LOOP construct built-in as an extension named VVM.  Classified as "Vertical-First".
+[^36]: Mitch Alsup's MyISA 66000 is available on request. A powerful RISC ISA with a **Hardware-level auto-vectorisation** LOOP built-in as an extension named VVM.  Classified as "Vertical-First".
 [^37]: MyISA 66000 has a CARRY register up to 64-bit. Repeated application of FMA or ADD (esp. within Auto-Vectored LOOPS) automatically and inherently creates big-int operations with zero effort.