From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 27 May 2020 19:22:13 +0000 (+0100)
Subject: remove write-block on register zero
X-Git-Tag: div_pipeline~780
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53c5229b0749c27c444af56efd5c185371f44760;p=soc.git

remove write-block on register zero
---

diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py
index 6653fa45..d0a7b540 100644
--- a/src/soc/regfile/regfile.py
+++ b/src/soc/regfile/regfile.py
@@ -68,7 +68,7 @@ class Register(Elaboratable):
                 else:
                     m.d.comb += rp.data_o.eq(reg)
 
-        # write ports, don't allow write to address 0 (ignore it)
+        # write ports, delayed by 1 cycle
         for wp in self._wrports:
             with m.If(wp.wen):
                 m.d.sync += reg.eq(wp.data_i)
@@ -203,9 +203,9 @@ class RegFile(Elaboratable):
                 with m.If(~wr_detect):
                     m.d.comb += rp.data_o.eq(regs[rp.raddr])
 
-        # write ports, don't allow write to address 0 (ignore it)
+        # write ports, delayed by one cycle
         for wp in self._wrports:
-            with m.If(wp.wen & (wp.waddr != Const(0, bsz))):
+            with m.If(wp.wen):
                 m.d.sync += regs[wp.waddr].eq(wp.data_i)
 
         return m