From: Florent Kermarrec Date: Sat, 20 Apr 2019 21:56:27 +0000 (+0200) Subject: boards: always define timing constraints the same way (1e9/freq_mhz) X-Git-Tag: 24jan2021_ls180~1314 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53c7be6e46a38d3e3c11045e774ea9bb5733cd9a;p=litex.git boards: always define timing constraints the same way (1e9/freq_mhz) --- diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py index 89f72120..083ab085 100644 --- a/litex/boards/platforms/genesys2.py +++ b/litex/boards/platforms/genesys2.py @@ -118,6 +118,6 @@ class Platform(XilinxPlatform): def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) try: - self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0) + self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6) except ConstraintError: pass diff --git a/litex/boards/platforms/kc705.py b/litex/boards/platforms/kc705.py index 498f3565..3948e5ad 100644 --- a/litex/boards/platforms/kc705.py +++ b/litex/boards/platforms/kc705.py @@ -553,15 +553,15 @@ set_property CONFIG_VOLTAGE 2.5 [current_design] def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) try: - self.add_period_constraint(self.lookup_request("clk200").p, 5.0) + self.add_period_constraint(self.lookup_request("clk200").p, 1e9/200e6) except ConstraintError: pass try: - self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0) + self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6) except ConstraintError: pass try: - self.add_period_constraint(self.lookup_request("eth_clocks").tx, 8.0) + self.add_period_constraint(self.lookup_request("eth_clocks").tx, 1e9/125e6) except ConstraintError: pass if isinstance(self.toolchain, XilinxISEToolchain): diff --git a/litex/boards/platforms/nexys_video.py b/litex/boards/platforms/nexys_video.py index 0844cce9..3ed2c0c1 100644 --- a/litex/boards/platforms/nexys_video.py +++ b/litex/boards/platforms/nexys_video.py @@ -239,6 +239,6 @@ class Platform(XilinxPlatform): def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) try: - self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0) + self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6) except ConstraintError: pass diff --git a/litex/boards/platforms/versa_ecp3.py b/litex/boards/platforms/versa_ecp3.py index ca9b6bd0..045f4d10 100644 --- a/litex/boards/platforms/versa_ecp3.py +++ b/litex/boards/platforms/versa_ecp3.py @@ -85,11 +85,11 @@ class Platform(LatticePlatform): def do_finalize(self, fragment): LatticePlatform.do_finalize(self, fragment) try: - self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0) + self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6) except ConstraintError: pass try: - self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0) + self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 1e9/125e6) except ConstraintError: pass diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py index 7d11e470..8368efa7 100644 --- a/litex/boards/platforms/versa_ecp5.py +++ b/litex/boards/platforms/versa_ecp5.py @@ -184,11 +184,11 @@ class Platform(LatticePlatform): def do_finalize(self, fragment): try: - self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0) + self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6) except ConstraintError: pass try: - self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0) + self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 1e9/125e6) except ConstraintError: pass diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index c5a20ea2..c6e90e45 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -104,8 +104,8 @@ class EthernetSoC(BaseSoC): self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 80.0) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 80.0) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 150f830b..7c8c331b 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -95,8 +95,8 @@ class EthernetSoC(BaseSoC): self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 0493db8c..3ad91e76 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -95,8 +95,8 @@ class EthernetSoC(BaseSoC): self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index db94b9f6..1e58f831 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -101,8 +101,8 @@ class EthernetSoC(BaseSoC): self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index 6331d4a1..e28ccb3e 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -41,7 +41,7 @@ class _CRG(Module): # clk / rst clk100 = platform.request("clk100") rst_n = platform.request("rst_n") - platform.add_period_constraint(clk100, 10.0) + platform.add_period_constraint(clk100, 1e9/100e6) # power on reset por_count = Signal(16, reset=2**16-1)