From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Fri, 10 Jul 2020 14:13:40 +0000 (+0200)
Subject: Add more R/W operations in test_soc
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53c9d38e6caa4171c0b86222a9868751e137b00c;p=gram.git

Add more R/W operations in test_soc
---

diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py
index 4d243b8..2c2fe43 100644
--- a/gram/test/test_soc.py
+++ b/gram/test/test_soc.py
@@ -170,11 +170,17 @@ class SocTestCase(FHDLTestCase):
 
             yield from wb_write(soc.bus, 0x10000000 >> 2, 0xF00DFACE, 0xF, 128)
             yield from wb_write(soc.bus, 0x10000004 >> 2, 0x12345678, 0xF, 128)
+            yield from wb_write(soc.bus, 0x10000008 >> 2, 0x00BA0BAB, 0xF, 128)
 
             res = yield from wb_read(soc.bus, 0x10000000 >> 2, 0xF, 128)
             self.assertEqual(res, 0xF00DFACE)
 
+            yield from wb_write(soc.bus, 0x10000008 >> 2, 0xCAFE1000, 0xF, 128)
+
             res = yield from wb_read(soc.bus, 0x10000004 >> 2, 0xF, 128)
             self.assertEqual(res, 0x12345678)
 
+            res = yield from wb_read(soc.bus, 0x10000008 >> 2, 0xF, 128)
+            self.assertEqual(res, 0xCAFE1000)
+
         runSimulation(m, process, "test_soc_interleaved_read_write.vcd")