From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Sep 2019 04:28:28 +0000 (-0700)
Subject: ffAmuxAB -> ffAenpol
X-Git-Tag: working-ls180~1039^2~190
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53ca536d674ade382da16adddfb02db7e970acef;p=yosys.git

ffAmuxAB -> ffAenpol
---

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 9291c2dfb..16a098fd0 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -83,9 +83,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
 			A.replace(Q, D);
 			if (st.ffAmux) {
 				SigSpec Y = st.ffAmux->getPort("\\Y");
-				SigSpec AB = st.ffAmux->getPort(st.ffAmuxAB == "\\A" ? "\\B" : "\\A");
+				SigSpec AB = st.ffAmux->getPort(st.ffAenpol ? "\\A" : "\\B");
 				A.replace(Y, AB);
-				cell->setPort("\\CEA2", st.ffAmux->getPort("\\S"));
+				SigSpec S = st.ffAmux->getPort("\\S");
+				cell->setPort("\\CEA2", st.ffAenpol ? S : pm.module->Not(NEW_ID, S));
 			}
 			else
 				cell->setPort("\\CEA2", State::S1);
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index fa490146c..579935869 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -2,7 +2,8 @@ pattern xilinx_dsp
 
 state <SigBit> clock
 state <SigSpec> sigA sigffAmux sigB sigffBmux sigC sigM sigP
-state <IdString> ffAmuxAB ffBmuxAB ffMmuxAB ffPmuxAB postAddAB postAddMuxAB
+state <IdString> ffBmuxAB ffMmuxAB ffPmuxAB postAddAB postAddMuxAB
+state <bool> ffAenpol
 
 match dsp
 	select dsp->type.in(\DSP48E1)
@@ -69,9 +70,10 @@ match ffAmux
 	filter GetSize(port(ffAmux, \Y)) >= GetSize(sigA)
 	slice offset GetSize(port(ffAmux, \Y))
 	filter offset+GetSize(sigA) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, \Y).extract(offset, GetSize(sigA)) == sigA
-	choice <IdString> AB {\A, \B}
-	filter offset+GetSize(sigffAmux) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, AB).extract(offset, GetSize(sigffAmux)) == sigffAmux
-	set ffAmuxAB AB
+	choice <IdString> BA {\B, \A}
+	filter offset+GetSize(sigffAmux) <= GetSize(port(ffAmux, \Y)) && port(ffAmux, BA).extract(offset, GetSize(sigffAmux)) == sigffAmux
+	define <bool> pol (BA == \B)
+	set ffAenpol pol
 	semioptional
 endmatch