From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 4 Jul 2022 11:46:07 +0000 (+0100)
Subject: add part III preamble
X-Git-Tag: opf_rfc_ls005_v1~1355
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53d2971973552fb9a1d14811e39692bfaf6c5eb8;p=libreriscv.git

add part III preamble
---

diff --git a/openpower/Makefile b/openpower/Makefile
index 6e90ef4f8..a6df1ffca 100755
--- a/openpower/Makefile
+++ b/openpower/Makefile
@@ -6,7 +6,7 @@ SOURCE_TEX := tex_out/remap.tex tex_out/bitmanip.tex tex_out/vector_ops.tex \
                 tex_out/pseudocode_fixedlogical.tex \
                 tex_out/pseudocode_svfixedarith.tex \
                 tex_out/big_integer_analysis.tex \
-                tex_out/vector_isas.tex 
+                tex_out/vector_isas.tex
 
 tex: $(SOURCE_TEX)
 	mkdir -p tex_out
diff --git a/openpower/simple_v_spec.tex b/openpower/simple_v_spec.tex
index 42605b57b..9cfee9545 100644
--- a/openpower/simple_v_spec.tex
+++ b/openpower/simple_v_spec.tex
@@ -225,11 +225,27 @@ Programme, requires full transparency.
 
 \part{Scalar Power ISA pseudocode}
 
+\chapter*{Preamble}
+\addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
+
 This section contains updated pseudocode from the Power ISA Specification
-v3.0B to be executable.  Several bugfixes have been created as a direct
-result.  A Formal Correctness Proof Research Paper written by Boris
+v3.0B to be executable.  Several bugfixes in Power ISA v3.0B have been
+found and reported as a direct result due to actually running the
+pseudocode as executable code in a Simulator.
+A Formal Correctness Proof Research Paper written by Boris
 Shingarov.
 
+Additionally, with SVP64 performing element-width over-rides it is the
+\textit{Scalar} pseudocode that needs adapting to variable-length
+(\textbf{XLEN}).  Maintaining duplicate identical copies in every
+respect \textit{except} for an XLEN as part of the Simple-V Specification
+is completely pointless and a waste of time: the updates to include
+XLEN need to be part
+of the Scalar Power ISA Specification.  This has the added benefit
+that it makes life much easier for 32-bit implementors, and has an
+additional benefit of making it possible for the Scalar Power ISA
+to extend to 128-bit in future (like RV128).
+
 \begin{appendices}
 \chapter{Fixed Point Arithmetic pseudocode}
 \hypertarget{svux2fpseudocode_fixedarith}{}