From: lkcl <lkcl@web>
Date: Sun, 20 Dec 2020 18:23:51 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1119
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53d457f3d2b2c858a7b326f1737973351da612e4;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 3d3c6eff8..77dab8158 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -33,8 +33,8 @@ Note that this is completely different from when VL=0.  VL=0 turns all operation
 # Register Naming
 
 SV Registers are simply the INT, FP and CR register files extended
-linearly to larger sizes.  Thus, the integer regfile in standard scalar
-OpenPOWER v3.0B and v3.1B is r0 to r31: SV extends this as r0 to r127.
+linearly to larger sizes.  Where the integer regfile in standard scalar
+OpenPOWER v3.0B and v3.1B is r0 to r31, SV extends this as r0 to r127.
 Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
 extended to 64 entries, CR0 thru CR63.