From: colepoirier <colepoirier@gmail.com>
Date: Sat, 16 May 2020 22:02:36 +0000 (-0700)
Subject: Made creation of Array of Signals in bperm.py more concise, changed
X-Git-Tag: div_pipeline~1121
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53e128fbd87d48e6de4b54b456d34b018e28218b;p=soc.git

Made creation of Array of Signals in bperm.py more concise, changed
string formatting to use python3 f"string{x}"
---

diff --git a/src/soc/logical/bperm.py b/src/soc/logical/bperm.py
index d312280d..518a4a81 100644
--- a/src/soc/logical/bperm.py
+++ b/src/soc/logical/bperm.py
@@ -36,13 +36,12 @@ class Bpermd(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         index = Signal(8, reset_less=True)
-        signals = [Signal(1, reset_less=True) for i in range(64)]
-        for i, n in enumerate(signals):
-            m.d.comb += n.eq(self.rb[i])
-        rb64 = Array(signals) # makes this indexable dynamically (a pmux)
+        rb64 = Array([Signal(1, reset_less=True, name=f"rb64_{i}") for i in range(64)])
+        for i in range(64):
+            m.d.comb += rb64[i].eq(self.rb[i])
         for i in range(8):
             index = self.rs[8*i:8*i+8]
-            idx = Signal(8, name="idx%d" % i, reset_less=True)
+            idx = Signal(8, name=f"idx_{i}", reset_less=True)
             m.d.comb += idx.eq(index)
             with m.If(idx < 64):
                 m.d.comb += self.perm[i].eq(rb64[idx])