From: Luke Kenneth Casson Leighton Date: Thu, 1 Apr 2021 22:24:00 +0000 (+0100) Subject: disable PLL so increase not-connected by another 4 pins X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53e2f90e9cdd76e241f5c1d5f5896ddbd25faac5;p=libresoc-litex.git disable PLL so increase not-connected by another 4 pins --- diff --git a/libresoc/ls180.py b/libresoc/ls180.py index 984755d..c9d1028 100644 --- a/libresoc/ls180.py +++ b/libresoc/ls180.py @@ -156,6 +156,7 @@ def io(): num_nc += 4 # mspi1 comments out, litex problems 25mar2021 num_nc += 6 # sd0 comments out, litex problems 25mar2021 num_nc += 2 # pwm comments out, litex problems 25mar2021 + num_nc += 4 # PLL disabled for now nc = ' '.join("NC%d" % i for i in range(num_nc)) _io.append(("nc", 0, Pins(nc), IOStandard("LVCMOS33")))