From: Alec Roelke <alec.roelke@gmail.com>
Date: Sun, 3 Mar 2019 20:13:51 +0000 (-0500)
Subject: arch-riscv: Implement MHARTID CSR
X-Git-Tag: v19.0.0.0~884
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53e74695ac28e02d10594af0ef6afff6536a0d35;p=gem5.git

arch-riscv: Implement MHARTID CSR

This patch implements the MHARTID CSR by intercepting attempts to access
it, similar to the way accesses to the performance counters are
intercepted, to return the thread's context ID.

Change-Id: Ie14a31036fbe0e49fb3347ac0c3c508d9427a10d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16988
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 4e36d5596..cc86752ab 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -112,6 +112,8 @@ RegVal
 ISA::readMiscReg(int misc_reg, ThreadContext *tc)
 {
     switch (misc_reg) {
+      case MISCREG_HARTID:
+        return tc->contextId();
       case MISCREG_CYCLE:
         if (hpmCounterEnabled(MISCREG_CYCLE)) {
             DPRINTF(RiscvMisc, "Cycle counter at: %llu.\n",