From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 13 Jan 2024 21:33:48 +0000 (+0000)
Subject: bug 676: closer to working maxloc. a lot of cr ops
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53eb96f06f15ecabf98096472149520e82829a22;p=openpower-isa.git

bug 676: closer to working maxloc. a lot of cr ops
---

diff --git a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
index f0bdca6b..831472cf 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
@@ -55,7 +55,7 @@ class DDFFirstTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
     def test_sv_maxloc_1(self):
-        self.sv_maxloc([0,6,7,8])
+        self.sv_maxloc([2,3,0,7])
 
     def tst_sv_maxloc_2(self):
         self.sv_maxloc([3,4,1,5])
@@ -86,19 +86,21 @@ class DDFFirstTestCase(FHDLTestCase):
                 #"addi 6, 0, 0",             # initialise r6 to zero
                 #"sv.lbzu/pi/dw=8 *6, 1(4)", # should be /lf here as well
                 # while (i<n and a[i]<=m) : i += 1
-                "sv.cmp/ff=lt/m=ge *0,0,*10,4", # truncates VL to min
+                "sv.cmp/ff=gt/m=ge *0,0,*10,4", # truncates VL to min
                 "sv.creqv *16,*16,*16", # set mask on already-tested
                 "setvl 2,0,4,0,1,1",        # set MVL=4, VL=MIN(MVL,CTR)
                 #"sv.addi/mr/sm=ge/dm=ns 4, *4, 0", # r4 = last non-masked value
                 "mtcrf 128, 0",       # clear CR0 (in case VL=0?)
-                "sv.minmax./ff=ge/m=ge 4, *10, 4, 1", # uses r4 as accumulator
-                "sv.svstep/mr 3, 0, 6, 1",  # svstep: get vector dststep
+                "sv.minmax./ff=lt/m=ge 4, *10, 4, 1", # uses r4 as accumulator
+                "sv.creqv *16,*16,*16", # set mask on already-tested
+                "sv.crand *19,*16,0", # set mask on less-than
+                "sv.cror *19,*19,2", # and equal 
+                "sv.svstep/mr/m=so 3, 0, 6, 1",  # svstep: get vector dststep
                 "add 1,1,3",  # accumulate dststep
                 #"sv.addi/dm=1<<r3 *5, 4, 0", # put r4 into vector at r5
-                "sv.creqv *16,*16,*16", # set mask on already-tested
-                #"bc 12,0, -0x34"            # CR0 lt bit clear, branch back
-                "setvl 3,0,4,0,1,1",        # set MVL=4, VL=MIN(MVL,CTR)
-                "sv.bc/m=ge 16, 19, -0x3c", # until r10[i]>r4 (and dec CTR)
+                "bc 12,0, -0x48"            # CR0 lt bit clear, branch back
+                #"setvl 3,0,4,0,1,1",        # set MVL=4, VL=MIN(MVL,CTR)
+                #"sv.bc/m=ge 16, 19, -0x3c", # until r10[i]>r4 (and dec CTR)
                         ])
         lst = list(lst)