From: lkcl <lkcl@web>
Date: Fri, 30 Aug 2019 10:37:51 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4185
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53f2a7a6c0ccef827431eb1b4b00c0d6002434c3;p=libreriscv.git

---

diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn
index 0c144fccf..be7db76a9 100644
--- a/simple_v_extension/specification/sv.setvl.mdwn
+++ b/simple_v_extension/specification/sv.setvl.mdwn
@@ -7,7 +7,7 @@ Thus it makes more sense to actually *use* one of the scalar registers *as* VL.
 
 Format for Vector Configuration Instructions under OP-V major opcode:
 
-| 31|30...20|19....15|14..12|11 7|6.....0| name       |
+| 31|30...20|19....15|14..12|11.7|6.....0| name       |
 |---|-------|--------|------|----|-------|------------|
 | 0 | VLMAX | rs1    | 111  | rd |1010111| sv.setvl   |
 | 0 | VLMAX | 0 (x0) | 111  | rd |1010111| sv.setvl   |