From: lkcl <lkcl@web>
Date: Mon, 2 Aug 2021 10:32:54 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~535
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53f70ae82b62f9ef593a14cfdff0bec99f1ec48b;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 6a5655d19..a27179676 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -148,3 +148,33 @@ Pseudocode for Horizontal-First Mode:
                if el_cond_ok:
                    break
 ```
+
+Pseudocode for Vertical-First Mode:
+
+```
+   new_srcstep, CRbits = SVSTATE_NEXT(srcstep)
+   if BO[0]:
+       cond_ok = 1
+   else
+       # select predicate bit or zero/one
+       if predicate[srcstep]:
+           # get SVP64 extended CR field 0..127
+           SVCRf = SVP64EXTRA(BI>>2)
+           CR{SVCRf+srcstep} = CRbits
+           testbit = CRbits[BI & 0b11]
+       else if not SVRMmode.sz:
+           SVSTATE.srcstep = new_srcstep
+           exit # no branch testing
+       else
+           testbit = SVRMmode.SNZ
+       # actual element test here
+       cond_ok <- ¬(testbit ^ BO[1])
+
+       # test for VL to be set (and exit)
+       if ~cond_ok and VLSET
+           if SVRMmode.VLI
+               SVSTATE.VL = new_srcstep+1
+           else
+               SVSTATE.VL = new_srcstep
+    SVSTATE.srcstep = new_srcstep
+```