From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 9 Apr 2020 21:31:14 +0000 (-0700)
Subject: aiger: -xaiger to read $_DFF_[NP]_ back with new clocks created
X-Git-Tag: working-ls180~549^2~70
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53fc3ed64563045949bcd52a03d2af586605d523;p=yosys.git

aiger: -xaiger to read $_DFF_[NP]_ back with new clocks created

according to mergeability class, and init state as cell attr
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 6fda92d73..7e5e6dd2d 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -454,6 +454,14 @@ void AigerReader::parse_xaiger()
 			for (unsigned i = 0; i < flopNum; i++)
 				mergeability.emplace_back(parse_xaiger_literal(f));
 		}
+		else if (c == 's') {
+			uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+			flopNum = parse_xaiger_literal(f);
+			log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
+			initial_state.reserve(flopNum);
+			for (unsigned i = 0; i < flopNum; i++)
+				initial_state.emplace_back(parse_xaiger_literal(f));
+		}
 		else if (c == 'n') {
 			parse_xaiger_literal(f);
 			f >> s;
@@ -767,6 +775,7 @@ void AigerReader::post_process()
 		}
 	}
 
+	dict<int, Wire*> mergeability_to_clock;
 	for (uint32_t i = 0; i < flopNum; i++) {
 		RTLIL::Wire *d = outputs[outputs.size() - flopNum + i];
 		log_assert(d);
@@ -778,10 +787,22 @@ void AigerReader::post_process()
 		log_assert(q->port_input);
 		q->port_input = false;
 
-		auto ff = module->addCell(NEW_ID, ID($__ABC9_FF_));
+		Cell* ff;
+		int clock_index = mergeability[i];
+		if (clock_index < 0) {
+			ff = module->addCell(NEW_ID, ID($_DFF_N_));
+			clock_index = -clock_index;
+		}
+		else if (clock_index > 0)
+			ff = module->addCell(NEW_ID, ID($_DFF_P_));
+		else log_abort();
+		auto r = mergeability_to_clock.insert(clock_index);
+		if (r.second)
+			r.first->second = module->addWire(NEW_ID);
+		ff->setPort(ID::C, r.first->second);
 		ff->setPort(ID::D, d);
 		ff->setPort(ID::Q, q);
-		ff->attributes[ID::abc9_mergeability] = mergeability[i];
+		ff->attributes[ID::abc9_init] = initial_state[i];
 	}
 
 	dict<RTLIL::IdString, std::pair<int,int>> wideports_cache;
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h
index 46ac81212..251a24977 100644
--- a/frontends/aiger/aigerparse.h
+++ b/frontends/aiger/aigerparse.h
@@ -45,7 +45,7 @@ struct AigerReader
     std::vector<RTLIL::Wire*> outputs;
     std::vector<RTLIL::Wire*> bad_properties;
     std::vector<RTLIL::Cell*> boxes;
-    std::vector<int> mergeability;
+    std::vector<int> mergeability, initial_state;
 
     AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
     void parse_aiger();