From: lkcl <lkcl@web>
Date: Mon, 11 Apr 2022 09:24:01 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2786
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=540523b8962ed59ed4a71640e2365e6dc0660478;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 11e9d58e4..e9a670218 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -709,7 +709,7 @@ so FP instructions with Rc=1 write to CR1 (n=1).
 
 CRs are not stored in SPRs: they are registers in their own right.
 Therefore context-switching the full set of CRs involves a Vectorised
-mfcr or mtcr, using VL=64, elwidth=8 to do so.  This is exactly as how
+mfcr or mtcr, using VL=8 to do so.  This is exactly as how
 scalar OpenPOWER context-switches CRs: it is just that there are now
 more of them.