From: lkcl <lkcl@web>
Date: Fri, 4 Jun 2021 18:59:54 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~792
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=54085f30f2afd887d2780e57b61d885c177782ba;p=libreriscv.git

---

diff --git a/openpower/sv/int_fp_mv/appendix.mdwn b/openpower/sv/int_fp_mv/appendix.mdwn
index c730ef38e..38a341ccf 100644
--- a/openpower/sv/int_fp_mv/appendix.mdwn
+++ b/openpower/sv/int_fp_mv/appendix.mdwn
@@ -35,6 +35,10 @@ rather than Double width hardcoded to 64 and Single width
 hardcoded to 32.  This allows a full range of conversions
 between FP64, FP32, FP16 and BF16.
 
+Note however that attempts to perform "Single" operations on
+FP16 elwidths will raise an illegal instruction trap: Half
+of FP16 is FP8, which is not defined as a legal IEEE754 format.
+
 # Simple-V SVP64 Saturation
 
 SVP64 also allows for Saturation, such that the result is truncated