From: lkcl <lkcl@web>
Date: Sat, 2 Jul 2022 10:15:07 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1413
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=541d5490a6c1db3d7911d9d64b6bb393806541c2;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 50939b6b5..f0ea713ae 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -128,10 +128,10 @@ from different sources is as follows:
 
 | condition           | effect         |
 | - | - |
-| `vf=1, RA=0, RT!=0` | VL,RT set to MIN(MVL, CTR)  |
-| `vf=1, RA=0, RT=0`  | VL set to MIN(MVL, SVi+1)  |
-| `vf=1, RA!=0, RT=0` | VL set to MIN(MVL, RA)  |
-| `vf=1, RA!=0, RT!=0` | VL,RT set to MIN(MVL, RA)  |
+| `vs=1, RA=0, RT!=0` | VL,RT set to MIN(MVL, CTR)  |
+| `vs=1, RA=0, RT=0`  | VL set to MIN(MVL, SVi+1)  |
+| `vs=1, RA!=0, RT=0` | VL set to MIN(MVL, RA)  |
+| `vs=1, RA!=0, RT!=0` | VL,RT set to MIN(MVL, RA)  |
 
 The reasoning here is that the opportunity to set RT equal to the
 immediate `SVi+1` is sacrificed in favour of setting from CTR.