From: Alan Lawrence Date: Mon, 17 Nov 2014 18:07:45 +0000 (+0000) Subject: aarch64-builtins.c (TYPES_CREATE): Remove. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=544009d369ebcdc8208b76ca4f7e3372f5985f5d;p=gcc.git aarch64-builtins.c (TYPES_CREATE): Remove. gcc/: * config/aarch64/aarch64-builtins.c (TYPES_CREATE): Remove. * config/aarch64/aarch64-simd-builtins.def (create): Remove. * config/aarch64/aarch64-simd.md (aarch64_create): Remove. * config/aarch64/arm_neon.h (vcreate_f64, vreinterpret_f64_s64, vreinterpret_f64_u64): Replace __builtin_aarch64_createv1df with C casts. * config/aarch64/iterators.md (VD1): Remove. gcc/testsuite/: * gcc.target/aarch64/simd/vfma_f64.c: Add asm volatile memory. * gcc.target/aarch64/simd/vfms_f64.c: Likewise. From-SVN: r217662 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ed4299ae956..d661ec12cf6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2014-11-17 Alan Lawrence + + * config/aarch64/aarch64-builtins.c (TYPES_CREATE): Remove. + * config/aarch64/aarch64-simd-builtins.def (create): Remove. + * config/aarch64/aarch64-simd.md (aarch64_create): Remove. + * config/aarch64/arm_neon.h (vcreate_f64, vreinterpret_f64_s64, + vreinterpret_f64_u64): Replace __builtin_aarch64_createv1df with C casts. + * config/aarch64/iterators.md (VD1): Remove. + 2014-11-17 Kyrylo Tkachov * config/aarch64/aarch64-cores.def (cortex-a53): Remove diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 87962f1f4f9..2637c71c3f4 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -138,7 +138,6 @@ static enum aarch64_type_qualifiers aarch64_types_unopu_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned }; #define TYPES_UNOPU (aarch64_types_unopu_qualifiers) -#define TYPES_CREATE (aarch64_types_unop_qualifiers) static enum aarch64_type_qualifiers aarch64_types_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_maybe_immediate }; diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 10bf67eb7c8..545c7da935e 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -39,7 +39,6 @@ 1-9 - CODE_FOR_<1-9> 10 - CODE_FOR_. */ - BUILTIN_VD1 (CREATE, create, 0) BUILTIN_VDC (COMBINE, combine, 0) BUILTIN_VB (BINOP, pmul, 0) BUILTIN_VDQF (UNOP, sqrt, 2) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 7f4d46ede51..148567b3b44 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2327,16 +2327,6 @@ ;; Patterns for AArch64 SIMD Intrinsics. -(define_expand "aarch64_create" - [(match_operand:VD1 0 "register_operand" "") - (match_operand:DI 1 "general_operand" "")] - "TARGET_SIMD" -{ - rtx src = gen_lowpart (mode, operands[1]); - emit_move_insn (operands[0], src); - DONE; -}) - ;; Lane extraction with sign extension to general purpose register. (define_insn "*aarch64_get_lane_extend" [(set (match_operand:GPI 0 "register_operand" "=r") diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index b3b80b8bc53..6200f625694 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -2638,7 +2638,7 @@ vcreate_u64 (uint64_t __a) __extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) vcreate_f64 (uint64_t __a) { - return __builtin_aarch64_createv1df (__a); + return (float64x1_t) __a; } __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__)) @@ -3238,7 +3238,7 @@ vreinterpret_f64_s32 (int32x2_t __a) __extension__ static __inline float64x1_t __attribute__((__always_inline__)) vreinterpret_f64_s64 (int64x1_t __a) { - return __builtin_aarch64_createv1df ((uint64_t) vget_lane_s64 (__a, 0)); + return (float64x1_t) __a; } __extension__ static __inline float64x1_t __attribute__((__always_inline__)) @@ -3262,7 +3262,7 @@ vreinterpret_f64_u32 (uint32x2_t __a) __extension__ static __inline float64x1_t __attribute__((__always_inline__)) vreinterpret_f64_u64 (uint64x1_t __a) { - return __builtin_aarch64_createv1df (vget_lane_u64 (__a, 0)); + return (float64x1_t) __a; } __extension__ static __inline float64x2_t __attribute__((__always_inline__)) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 99351679794..7dd39179be7 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -147,9 +147,6 @@ ;; Double vector modes for combines. (define_mode_iterator VDIC [V8QI V4HI V2SI]) -;; Double vector modes inc V1DF -(define_mode_iterator VD1 [V8QI V4HI V2SI V2SF V1DF]) - ;; Vector modes except double int. (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 46ab25f8980..6c25013c34a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2014-11-17 Alan Lawrence + + * gcc.target/aarch64/simd/vfma_f64.c: Add asm volatile memory. + * gcc.target/aarch64/simd/vfms_f64.c: Likewise. + 2014-11-17 Ilya Enkovich * gcc.target/i386/chkp-strlen-1.c: New. diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vfma_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vfma_f64.c index 272b79ceb39..8083d2c0d68 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/vfma_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/vfma_f64.c @@ -7,6 +7,10 @@ #define EPS 1.0e-15 +#define INHIB_OPT(x) asm volatile ("mov %d0, %1.d[0]" \ + : "=w"(x) \ + : "w"(x) \ + : /* No clobbers. */); extern void abort (void); @@ -24,6 +28,10 @@ main (void) arg2 = vcreate_f64 (0x3fa88480812d6670ULL); arg3 = vcreate_f64 (0x3fd5791ae2a92572ULL); + INHIB_OPT (arg1); + INHIB_OPT (arg2); + INHIB_OPT (arg3); + expected = 0.6280448184360076; actual = vget_lane_f64 (vfma_f64 (arg1, arg2, arg3), 0); diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vfms_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vfms_f64.c index f6e1f77886d..ede140d7538 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/vfms_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/vfms_f64.c @@ -7,6 +7,10 @@ #define EPS 1.0e-15 +#define INHIB_OPT(x) asm volatile ("mov %d0, %1.d[0]" \ + : "=w"(x) \ + : "w"(x) \ + : /* No clobbers. */); extern void abort (void); @@ -24,6 +28,10 @@ main (void) arg2 = vcreate_f64 (0x3fe6b78680fa29ceULL); arg3 = vcreate_f64 (0x3feea3cbf921fbe0ULL); + INHIB_OPT (arg1); + INHIB_OPT (arg2); + INHIB_OPT (arg3); + expected = 4.4964705746355915e-2; actual = vget_lane_f64 (vfms_f64 (arg1, arg2, arg3), 0);