From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Apr 2019 00:52:42 +0000 (+0100)
Subject: replace n_o_valid with d_valid
X-Git-Tag: ls180-24jan2020~1329
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=54561aab54fe555cc8650aa37d608fd63ea96620;p=ieee754fpu.git

replace n_o_valid with d_valid
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index f88907e1..668877be 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -222,23 +222,22 @@ class NextControl:
         self._o_valid = Signal(name="n_o_valid") # self out>>  next
         self.i_ready = Signal(name="n_i_ready") # self <<in   next
         self.o_data = None # XXX MUST BE ADDED BY USER
-        if stage_ctl:
-            self.s_o_valid = Signal(name="n_s_o_vld") # self out>>  next
+        self.d_valid = Signal(reset=1) # INTERNAL (data valid)
 
     @property
     def o_valid(self):
         """ public-facing API: indicates (externally) that data is valid
         """
+        return self._o_valid
         if self.stage_ctl:
             return self.s_o_valid
-        return self._o_valid
 
     def i_ready_logic(self):
         """ public-facing API: receives indication that transmit is possible
         """
+        return self.i_ready
         if self.stage_ctl:
             return self.i_ready & self.s_o_valid
-        return self.i_ready
 
     def connect_to_next(self, nxt):
         """ helper function to connect to the next stage data/valid/ready.
@@ -545,12 +544,9 @@ class ControlBase:
         with m.Else():
             m.d.comb += self.p.s_o_ready.eq(0)
 
-        # when the pipeline (buffered or otherwise) says "valid",
-        # test the *stage* "valid".
-        with m.If(self.n._o_valid):
-            m.d.comb += self.n.s_o_valid.eq(self.stage.n_o_valid)
-        with m.Else():
-            m.d.comb += self.n.s_o_valid.eq(0)
+        # bring data valid into n-control
+        m.d.comb += self.n.d_valid.eq(self.stage.d_valid)
+
         return m
 
 
diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 28a48db4..be2f2a43 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -597,10 +597,12 @@ class ExampleStageDelayCls(StageCls):
 
     @property
     def p_o_ready(self):
+        return Const(1)
         return self.count == 0
 
     @property
-    def n_o_valid(self):
+    def d_valid(self):
+        return self.count == 2
         return Const(1)
 
     def process(self, i):
@@ -656,8 +658,8 @@ def data_chain1():
 def test12_resultfn(o_data, expected, i, o):
     res = expected + 1
     assert o_data == res, \
-                "%d-%d data %x not match %s\n" \
-                % (i, o, o_data, repr(expected))
+                "%d-%d data %x not match %x\n" \
+                % (i, o, o_data, res)