From: whitequark <whitequark@whitequark.org>
Date: Thu, 11 Jun 2020 16:19:40 +0000 (+0000)
Subject: back.cxxrtl: new backend.
X-Git-Tag: working2~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=545e49c2;p=nmigen.git

back.cxxrtl: new backend.
---

diff --git a/nmigen/back/cxxrtl.py b/nmigen/back/cxxrtl.py
new file mode 100644
index 0000000..8010539
--- /dev/null
+++ b/nmigen/back/cxxrtl.py
@@ -0,0 +1,27 @@
+from .._yosys import *
+from . import rtlil
+
+
+__all__ = ["YosysError", "convert", "convert_fragment"]
+
+
+def _convert_rtlil_text(rtlil_text, *, src_loc_at=0):
+     # FIXME: update this requirement once Yosys updates its node version
+    yosys = find_yosys(lambda ver: ver >= (0, 9))
+    return yosys.run(["-q", "-"], """
+read_ilang <<rtlil
+{}
+rtlil
+delete w:$verilog_initial_trigger
+write_cxxrtl
+""".format(rtlil_text), src_loc_at=1 + src_loc_at)
+
+
+def convert_fragment(*args, **kwargs):
+    rtlil_text, name_map = rtlil.convert_fragment(*args, **kwargs)
+    return _convert_rtlil_text(rtlil_text, src_loc_at=1), name_map
+
+
+def convert(*args, **kwargs):
+    rtlil_text = rtlil.convert(*args, **kwargs)
+    return _convert_rtlil_text(rtlil_text, src_loc_at=1)
diff --git a/nmigen/cli.py b/nmigen/cli.py
index e530692..a3ae326 100644
--- a/nmigen/cli.py
+++ b/nmigen/cli.py
@@ -1,7 +1,7 @@
 import argparse
 
 from .hdl.ir import Fragment
-from .back import rtlil, verilog, pysim
+from .back import rtlil, cxxrtl, verilog, pysim
 
 
 __all__ = ["main"]
@@ -16,7 +16,7 @@ def main_parser(parser=None):
     p_generate = p_action.add_parser("generate",
         help="generate RTLIL or Verilog from the design")
     p_generate.add_argument("-t", "--type", dest="generate_type",
-        metavar="LANGUAGE", choices=["il", "v"],
+        metavar="LANGUAGE", choices=["il", "cc", "v"],
         default=None,
         help="generate LANGUAGE (il for RTLIL, v for Verilog; default: %(default)s)")
     p_generate.add_argument("generate_file",
@@ -46,14 +46,18 @@ def main_runner(parser, args, design, platform=None, name="top", ports=()):
         fragment = Fragment.get(design, platform)
         generate_type = args.generate_type
         if generate_type is None and args.generate_file:
-            if args.generate_file.name.endswith(".v"):
-                generate_type = "v"
             if args.generate_file.name.endswith(".il"):
                 generate_type = "il"
+            if args.generate_file.name.endswith(".cc"):
+                generate_type = "cc"
+            if args.generate_file.name.endswith(".v"):
+                generate_type = "v"
         if generate_type is None:
             parser.error("specify file type explicitly with -t")
         if generate_type == "il":
             output = rtlil.convert(fragment, name=name, ports=ports)
+        if generate_type == "cc":
+            output = cxxrtl.convert(fragment, name=name, ports=ports)
         if generate_type == "v":
             output = verilog.convert(fragment, name=name, ports=ports)
         if args.generate_file: