From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 1 Jul 2019 18:50:14 +0000 (-0700)
Subject: Capture all data in one "abc_flop" attribute
X-Git-Tag: working-ls180~881^2^2~287
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5466121ffb055c81946f8a729724febb8f93d4ef;p=yosys.git

Capture all data in one "abc_flop" attribute
---

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 9f6f9c47e..a91720260 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -23,7 +23,7 @@
 module \$__ABC_FF_ (input C, D, output Q);
 endmodule
 
-(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *)
+(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
 module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
   parameter [0:0] INIT = 1'b0;
   //parameter [0:0] IS_C_INVERTED = 1'b0;