From: Cole Poirier Date: Sat, 29 Aug 2020 22:56:15 +0000 (-0700) Subject: mmu.py, dcache.py, mem_types.py change types capitalization because I X-Git-Tag: semi_working_ecp5~228 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=546ee4265b1fc686d56c425e8083d91d3ae0b3ea;p=soc.git mmu.py, dcache.py, mem_types.py change types capitalization because I was making typing errors, and this make more sense. Mmu -> MMU, Dcache -> DCache, Icache -> ICache --- diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 872cbca1..3ac38987 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1,4 +1,4 @@ -"""Dcache +"""DCache based on Anton Blanchard microwatt dcache.vhdl @@ -12,10 +12,10 @@ from nmigen.cli import main from nmigen.iocontrol import RecordObject from nmigen.util import log2_int -from experiment.mem_types import LoadStore1ToDcacheType, - DcacheToLoadStore1Type, - MmuToDcacheType, - DcacheToMmuType +from experiment.mem_types import LoadStore1ToDCacheType, + DCacheToLoadStore1Type, + MMUToDCacheType, + DCacheToMMUType from experiment.wb_types import WB_ADDR_BITS, WB_DATA_BITS, WB_SEL_BITS, WBAddrType, WBDataType, WBSelType, @@ -88,7 +88,7 @@ class State(Enum): class RegStage0(RecordObject): def __init__(self): super().__init__() - self.req = LoadStore1ToDcacheType() + self.req = LoadStore1ToDCacheType() self.tlbie = Signal() self.doall = Signal() self.tlbld = Signal() @@ -185,9 +185,9 @@ class Reservation(RecordObject): # * Complete load misses on the cycle when WB data comes instead of # at the end of line (this requires dealing with requests coming in # while not idle...) -class Dcache(Elaboratable): +class DCache(Elaboratable): def __init__(self): - # TODO: make these parameters of Dcache at some point + # TODO: make these parameters of DCache at some point self.LINE_SIZE = 64 # Line size in bytes self.NUM_LINES = 32 # Number of lines in a set self.NUM_WAYS = 4 # Number of ways @@ -196,11 +196,11 @@ class Dcache(Elaboratable): self.TLB_LG_PGSZ = 12 # L1 DTLB log_2(page_size) self.LOG_LENGTH = 0 # Non-zero to enable log data collection - self.d_in = LoadStore1ToDcacheType() - self.d_out = DcacheToLoadStore1Type() + self.d_in = LoadStore1ToDCacheType() + self.d_out = DCacheToLoadStore1Type() - self.m_in = MmuToDcacheType() - self.m_out = DcacheToMmuType() + self.m_in = MMUToDCacheType() + self.m_out = DCacheToMMUType() self.stall_out = Signal() @@ -2724,7 +2724,7 @@ def dcache_sim(dut): def test_dcache(): - dut = Dcache() + dut = DCache() vl = rtlil.convert(dut, ports=[]) with open("test_dcache.il", "w") as f: f.write(vl) diff --git a/src/soc/experiment/mem_types.py b/src/soc/experiment/mem_types.py index ed7b411f..c0feb1e3 100644 --- a/src/soc/experiment/mem_types.py +++ b/src/soc/experiment/mem_types.py @@ -7,7 +7,7 @@ from nmutil.iocontrol import RecordObject from nmigen import Signal -class DcacheToLoadStore1Type(RecordObject): +class DCacheToLoadStore1Type(RecordObject): def __init__(self): super().__init__() self.valid = Signal() @@ -17,7 +17,7 @@ class DcacheToLoadStore1Type(RecordObject): self.cache_paradox = Signal() -class DcacheToMmuType(RecordObject): +class DCacheToMMUType(RecordObject): def __init__(self): super().__init__() self.stall = Signal() @@ -25,7 +25,7 @@ class DcacheToMmuType(RecordObject): self.err = Signal() self.data = Signal(64) -class Fetch1ToIcacheType(RecordObject): +class Fetch1ToICacheType(RecordObject): def __init__(self): super().__init__() self.req = Signal() @@ -35,7 +35,7 @@ class Fetch1ToIcacheType(RecordObject): self.sequential = Signal() self.nia = Signal(64) -class IcacheToDecode1Type(RecordObject): +class ICacheToDecode1Type(RecordObject): def __init__(self): super().__init__() self.valid = Signal() @@ -44,7 +44,7 @@ class IcacheToDecode1Type(RecordObject): self.nia = Signal(64) self.insn = Signal(32) -class LoadStore1ToDcacheType(RecordObject): +class LoadStore1ToDCacheType(RecordObject): def __init__(self): super().__init__() self.valid = Signal() @@ -59,7 +59,7 @@ class LoadStore1ToDcacheType(RecordObject): self.data = Signal() self.byte_sel = Signal() -class LoadStore1ToMmuType(RecordObject): +class LoadStore1ToMMUType(RecordObject): def __init__(self): super().__init__() self.valid = Signal() @@ -73,7 +73,7 @@ class LoadStore1ToMmuType(RecordObject): self.addr = Signal(64) self.rs = Signal(64) -class MmuToLoadStore1Type(RecordObject): +class MMUToLoadStore1Type(RecordObject): def __init__(self): super().__init__() self.done = Signal() @@ -85,7 +85,7 @@ class MmuToLoadStore1Type(RecordObject): self.rc_error = Signal() self.sprval = Signal(64) -class MmuToDcacheType(RecordObject): +class MMUToDCacheType(RecordObject): def __init__(self): super().__init__() self.valid = Signal() @@ -95,7 +95,7 @@ class MmuToDcacheType(RecordObject): self.addr = Signal(64) self.pte = Signal(64) -class MmuToIcacheType(RecordObject): +class MMUToICacheType(RecordObject): def __init__(self): super().__init__() self.tlbld = Signal() diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py index de1c8c85..1fab47a4 100644 --- a/src/soc/experiment/mmu.py +++ b/src/soc/experiment/mmu.py @@ -12,11 +12,11 @@ from nmutil.byterev import byte_reverse from nmutil.mask import Mask -from soc.experiment.mem_types import (LoadStore1ToMmuType, - MmuToLoadStore1Type, - MmuToDcacheType, - DcacheToMmuType, - MmuToIcacheType) +from soc.experiment.mem_types import (LoadStore1ToMMUType, + MMUToLoadStore1Type, + MMUToDCacheType, + DCacheToMMUType, + MMUToICacheType) @unique @@ -73,11 +73,11 @@ class MMU(Elaboratable): (i.e. there is no gRA -> hRA translation). """ def __init__(self): - self.l_in = LoadStore1ToMmuType() - self.l_out = MmuToLoadStore1Type() - self.d_out = MmuToDcacheType() - self.d_in = DcacheToMmuType() - self.i_out = MmuToIcacheType() + self.l_in = LoadStore1ToMMUType() + self.l_out = MMUToLoadStore1Type() + self.d_out = MMUToDCacheType() + self.d_in = DCacheToMMUType() + self.i_out = MMUToICacheType() def radix_tree_idle(self, m, l_in, r, v): comb = m.d.comb