From: Mike Frysinger Date: Wed, 19 May 2021 01:54:36 +0000 (-0400) Subject: opcodes: cris: move desc & opc files from sim/ X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=547112801156ff51bbb44f86dd9a2ca4b4723d41;p=binutils-gdb.git opcodes: cris: move desc & opc files from sim/ All other cgen ports keep their generated desc & opc files under opcodes/, so move the cris files over too. The cris-opc.c file, while not generated, is already here to complement. --- diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 11896df782a..263529ebcfb 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,14 @@ +2021-05-24 Mike Frysinger + + * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h. + (TARGET_LIBOPCODES_CFILES): Add cris-desc.c. + (CGEN_CPUS): Add cris. + (CRIS_DEPS): Define. + (stamp-cris): New rule. + * cgen.sh: Handle desc action. + * configure.ac (bfd_cris_arch): Add cris-desc.lo. + * Makefile.in, configure: Regenerate. + 2021-05-18 Job Noorman PR 27814 diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index 04980f36b11..ddae8bd9052 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -60,6 +60,7 @@ BUILD_LIB_DEPS = @BUILD_LIB_DEPS@ HFILES = \ aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \ bpf-desc.h bpf-opc.h \ + cris-desc.h cris-opc.h \ epiphany-desc.h epiphany-opc.h \ fr30-desc.h fr30-opc.h \ frv-desc.h frv-opc.h \ @@ -108,6 +109,7 @@ TARGET_LIBOPCODES_CFILES = \ cgen-opc.c \ cr16-dis.c \ cr16-opc.c \ + cris-desc.c \ cris-dis.c \ cris-opc.c \ crx-dis.c \ @@ -371,10 +373,11 @@ CGENDEPS = \ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in -CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xc16x xstormy16 +CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xc16x xstormy16 if CGEN_MAINT BPF_DEPS = stamp-bpf +CRIS_DEPS = stamp-cris EPIPHANY_DEPS = stamp-epiphany FR30_DEPS = stamp-fr30 FRV_DEPS = stamp-frv @@ -390,6 +393,7 @@ XC16X_DEPS = stamp-xc16x XSTORMY16_DEPS = stamp-xstormy16 else BPF_DEPS = +CRIS_DEPS = EPIPHANY_DEPS = FR30_DEPS = FRV_DEPS = @@ -431,6 +435,15 @@ stamp-bpf: $(CGENDEPS) $(CPUDIR)/bpf.cpu $(CPUDIR)/bpf.opc $(MAKE) run-cgen arch=bpf prefix=bpf \ archfile=$(CPUDIR)/bpf.cpu opcfile=$(CPUDIR)/bpf.opc +$(srcdir)/cris-desc.h $(srcdir)/cris-desc.c $(srcdir)/cris-opc.h: $(CRIS_DEPS) + @true + +stamp-cris: $(CGENDEPS) $(CPUDIR)/cris.cpu + $(SHELL) $(srcdir)/cgen.sh desc $(srcdir) $(CGEN) \ + $(CGENDIR) "$(CGENFLAGS)" cris cris $(CPUDIR)/cris.cpu /dev/null \ + "$(options)" "$(extrafiles)" + touch $@ + $(srcdir)/epiphany-desc.h $(srcdir)/epiphany-desc.c $(srcdir)/epiphany-opc.h \ $(srcdir)/epiphany-opc.c $(srcdir)/epiphany-ibld.c \ $(srcdir)/epiphany-opinst.c $(srcdir)/epiphany-asm.c \ diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index b2965ba70cd..23a52bcd69a 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -450,6 +450,7 @@ BFD_H = ../bfd/bfd.h HFILES = \ aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \ bpf-desc.h bpf-opc.h \ + cris-desc.h cris-opc.h \ epiphany-desc.h epiphany-opc.h \ fr30-desc.h fr30-opc.h \ frv-desc.h frv-opc.h \ @@ -499,6 +500,7 @@ TARGET_LIBOPCODES_CFILES = \ cgen-opc.c \ cr16-dis.c \ cr16-opc.c \ + cris-desc.c \ cris-dis.c \ cris-opc.c \ crx-dis.c \ @@ -729,9 +731,11 @@ CGENDEPS = \ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in -CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xc16x xstormy16 +CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xc16x xstormy16 @CGEN_MAINT_FALSE@BPF_DEPS = @CGEN_MAINT_TRUE@BPF_DEPS = stamp-bpf +@CGEN_MAINT_FALSE@CRIS_DEPS = +@CGEN_MAINT_TRUE@CRIS_DEPS = stamp-cris @CGEN_MAINT_FALSE@EPIPHANY_DEPS = @CGEN_MAINT_TRUE@EPIPHANY_DEPS = stamp-epiphany @CGEN_MAINT_FALSE@FR30_DEPS = @@ -915,6 +919,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen-opc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cr16-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cr16-opc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cris-desc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cris-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cris-opc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/crx-dis.Plo@am__quote@ @@ -1417,6 +1422,15 @@ stamp-bpf: $(CGENDEPS) $(CPUDIR)/bpf.cpu $(CPUDIR)/bpf.opc $(MAKE) run-cgen arch=bpf prefix=bpf \ archfile=$(CPUDIR)/bpf.cpu opcfile=$(CPUDIR)/bpf.opc +$(srcdir)/cris-desc.h $(srcdir)/cris-desc.c $(srcdir)/cris-opc.h: $(CRIS_DEPS) + @true + +stamp-cris: $(CGENDEPS) $(CPUDIR)/cris.cpu + $(SHELL) $(srcdir)/cgen.sh desc $(srcdir) $(CGEN) \ + $(CGENDIR) "$(CGENFLAGS)" cris cris $(CPUDIR)/cris.cpu /dev/null \ + "$(options)" "$(extrafiles)" + touch $@ + $(srcdir)/epiphany-desc.h $(srcdir)/epiphany-desc.c $(srcdir)/epiphany-opc.h \ $(srcdir)/epiphany-opc.c $(srcdir)/epiphany-ibld.c \ $(srcdir)/epiphany-opinst.c $(srcdir)/epiphany-asm.c \ diff --git a/opcodes/cgen.sh b/opcodes/cgen.sh index bdcc56df687..cf6a5f112a6 100644 --- a/opcodes/cgen.sh +++ b/opcodes/cgen.sh @@ -175,6 +175,40 @@ opcodes) rm -f ${tmp}-asm.in1 ${tmp}-dis.in1 ;; +desc) + # For ports that only generate the desc module & opc header. + rm -f ${tmp}-desc.h1 ${tmp}-desc.h + rm -f ${tmp}-desc.c1 ${tmp}-desc.c + rm -f ${tmp}-opc.h1 ${tmp}-opc.h + + ${cgen} ${cgendir}/cgen-opc.scm \ + -s ${cgendir} \ + ${cgenflags} \ + -OPC ${opcfile} \ + -f "${archflags}" \ + -m all \ + -a ${archfile} \ + -i all \ + -H ${tmp}-desc.h1 \ + -C ${tmp}-desc.c1 \ + -O ${tmp}-opc.h1 + + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/g" \ + < ${tmp}-desc.h1 > ${tmp}-desc.h + ${rootdir}/move-if-change ${tmp}-desc.h ${srcdir}/${arch}-desc.h + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/g" \ + < ${tmp}-desc.c1 > ${tmp}-desc.c + ${rootdir}/move-if-change ${tmp}-desc.c ${srcdir}/${arch}-desc.c + sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ + -e "s/@prefix@/${prefix}/g" \ + < ${tmp}-opc.h1 > ${tmp}-opc.h + ${rootdir}/move-if-change ${tmp}-opc.h ${srcdir}/${arch}-opc.h + + rm -f ${tmp}-desc.h1 ${tmp}-desc.c1 ${tmp}-opc.h1 + ;; + *) echo "$0: bad action: ${action}" >&2 exit 1 diff --git a/opcodes/configure b/opcodes/configure index 922a939125b..470231ebc80 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -12216,7 +12216,7 @@ if test x${all_targets} = xfalse ; then bfd_avr_arch) ta="$ta avr-dis.lo" ;; bfd_bfin_arch) ta="$ta bfin-dis.lo" ;; bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;; - bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;; + bfd_cris_arch) ta="$ta cris-desc.lo cris-dis.lo cris-opc.lo cgen-bitset.lo" ;; bfd_crx_arch) ta="$ta crx-dis.lo crx-opc.lo" ;; bfd_csky_arch) ta="$ta csky-dis.lo" ;; bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;; diff --git a/opcodes/configure.ac b/opcodes/configure.ac index 911c9c6f082..e564f067334 100644 --- a/opcodes/configure.ac +++ b/opcodes/configure.ac @@ -277,7 +277,7 @@ if test x${all_targets} = xfalse ; then bfd_avr_arch) ta="$ta avr-dis.lo" ;; bfd_bfin_arch) ta="$ta bfin-dis.lo" ;; bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;; - bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;; + bfd_cris_arch) ta="$ta cris-desc.lo cris-dis.lo cris-opc.lo cgen-bitset.lo" ;; bfd_crx_arch) ta="$ta crx-dis.lo crx-opc.lo" ;; bfd_csky_arch) ta="$ta csky-dis.lo" ;; bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;; diff --git a/opcodes/cris-desc.c b/opcodes/cris-desc.c new file mode 100644 index 00000000000..78302e11bbd --- /dev/null +++ b/opcodes/cris-desc.c @@ -0,0 +1,2783 @@ +/* CPU data for cris. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2021 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, see . + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "cris-desc.h" +#include "cris-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "crisv0", MACH_CRISV0 }, + { "crisv3", MACH_CRISV3 }, + { "crisv8", MACH_CRISV8 }, + { "crisv10", MACH_CRISV10 }, + { "crisv32", MACH_CRISV32 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "cris", ISA_CRIS }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE cris_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE cris_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE cris_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE cris_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA cris_cgen_isa_table[] = { + { "cris", 16, 16, 16, 48 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH cris_cgen_mach_table[] = { + { "crisv0", "cris", MACH_CRISV0, 0 }, + { "crisv3", "cris", MACH_CRISV3, 0 }, + { "crisv8", "cris", MACH_CRISV8, 0 }, + { "crisv10", "cris", MACH_CRISV10, 0 }, + { "crisv32", "crisv32", MACH_CRISV32, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_pcreg_entries[] = +{ + { "PC", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "SP", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "R0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "R1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "R2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "R3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "R4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "R5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "R6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "R7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "R8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "R9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "R10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "R11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "R12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "R13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "R14", 14, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg = +{ + & cris_cgen_opval_gr_names_pcreg_entries[0], + 17, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_acr_entries[] = +{ + { "ACR", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "SP", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "R0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "R1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "R2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "R3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "R4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "R5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "R6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "R7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "R8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "R9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "R10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "R11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "R12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "R13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "R14", 14, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD cris_cgen_opval_gr_names_acr = +{ + & cris_cgen_opval_gr_names_acr_entries[0], + 17, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_v32_entries[] = +{ + { "ACR", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "SP", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "R0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "R1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "R2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "R3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "R4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "R5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "R6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "R7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "R8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "R9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "R10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "R11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "R12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "R13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "R14", 14, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD cris_cgen_opval_gr_names_v32 = +{ + & cris_cgen_opval_gr_names_v32_entries[0], + 17, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v10_entries[] = +{ + { "CCR", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "MOF", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "IBR", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "IRP", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "BAR", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "DCCR", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "BRP", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "USP", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "VR", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "SRP", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "P0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "P1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "P2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "P3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "P4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "P5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "P6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "P7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "P8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "P9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "P10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "P11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "P12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "P13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "P14", 14, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD cris_cgen_opval_p_names_v10 = +{ + & cris_cgen_opval_p_names_v10_entries[0], + 25, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v32_entries[] = +{ + { "BZ", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "PID", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "SRS", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "WZ", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "EXS", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "EDA", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "MOF", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "DZ", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "EBP", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "ERP", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "NRP", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "CCS", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "USP", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "SPC", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "VR", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "SRP", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "P0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "P1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "P2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "P3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "P4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "P5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "P6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "P7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "P8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "P9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "P10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "P11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "P12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "P13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "P14", 14, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD cris_cgen_opval_p_names_v32 = +{ + & cris_cgen_opval_p_names_v32_entries[0], + 31, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v32_x_entries[] = +{ + { "BZ", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "PID", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "SRS", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "WZ", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "EXS", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "EDA", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "MOF", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "DZ", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "EBP", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "ERP", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "NRP", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "CCS", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "USP", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "SPC", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "VR", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "SRP", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "P0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "P1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "P2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "P3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "P4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "P5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "P6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "P7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "P8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "P9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "P10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "P11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "P12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "P13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "P14", 14, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD cris_cgen_opval_p_names_v32_x = +{ + & cris_cgen_opval_p_names_v32_x_entries[0], + 31, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_inc_entries[] = +{ + { "", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "+", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD cris_cgen_opval_h_inc = +{ + & cris_cgen_opval_h_inc_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_ccode_entries[] = +{ + { "cc", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "cs", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "eq", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "vc", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "vs", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "pl", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "mi", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "ls", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "hi", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "ge", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "le", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "a", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "wf", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD cris_cgen_opval_h_ccode = +{ + & cris_cgen_opval_h_ccode_entries[0], + 16, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_swap_entries[] = +{ + { " ", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "b", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "br", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "w", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "wr", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "wb", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "wbr", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "nr", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "nb", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "nbr", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "nw", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "nwr", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "nwb", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "nwbr", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD cris_cgen_opval_h_swap = +{ + & cris_cgen_opval_h_swap_entries[0], + 16, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_flagbits_entries[] = +{ + { "_", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "v", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "cv", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cz", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "vz", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "cvz", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "cn", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "vn", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "cvn", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "zn", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "czn", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "vzn", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzn", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "x", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "cx", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "vx", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "cvx", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "zx", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "czx", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "vzx", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzx", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "nx", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "cnx", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "vnx", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "cvnx", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "znx", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "cznx", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "vznx", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "cvznx", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "i", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "ci", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "vi", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "cvi", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "zi", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "czi", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "vzi", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzi", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "ni", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "cni", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "vni", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "cvni", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "zni", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "czni", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "vzni", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzni", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "xi", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "cxi", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "vxi", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "cvxi", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "zxi", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "czxi", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "vzxi", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzxi", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "nxi", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "cnxi", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "vnxi", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "cvnxi", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "znxi", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "cznxi", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "vznxi", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "cvznxi", 63, {0, {{{0, 0}}}}, 0, 0 }, + { "u", 64, {0, {{{0, 0}}}}, 0, 0 }, + { "cu", 65, {0, {{{0, 0}}}}, 0, 0 }, + { "vu", 66, {0, {{{0, 0}}}}, 0, 0 }, + { "cvu", 67, {0, {{{0, 0}}}}, 0, 0 }, + { "zu", 68, {0, {{{0, 0}}}}, 0, 0 }, + { "czu", 69, {0, {{{0, 0}}}}, 0, 0 }, + { "vzu", 70, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzu", 71, {0, {{{0, 0}}}}, 0, 0 }, + { "nu", 72, {0, {{{0, 0}}}}, 0, 0 }, + { "cnu", 73, {0, {{{0, 0}}}}, 0, 0 }, + { "vnu", 74, {0, {{{0, 0}}}}, 0, 0 }, + { "cvnu", 75, {0, {{{0, 0}}}}, 0, 0 }, + { "znu", 76, {0, {{{0, 0}}}}, 0, 0 }, + { "cznu", 77, {0, {{{0, 0}}}}, 0, 0 }, + { "vznu", 78, {0, {{{0, 0}}}}, 0, 0 }, + { "cvznu", 79, {0, {{{0, 0}}}}, 0, 0 }, + { "xu", 80, {0, {{{0, 0}}}}, 0, 0 }, + { "cxu", 81, {0, {{{0, 0}}}}, 0, 0 }, + { "vxu", 82, {0, {{{0, 0}}}}, 0, 0 }, + { "cvxu", 83, {0, {{{0, 0}}}}, 0, 0 }, + { "zxu", 84, {0, {{{0, 0}}}}, 0, 0 }, + { "czxu", 85, {0, {{{0, 0}}}}, 0, 0 }, + { "vzxu", 86, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzxu", 87, {0, {{{0, 0}}}}, 0, 0 }, + { "nxu", 88, {0, {{{0, 0}}}}, 0, 0 }, + { "cnxu", 89, {0, {{{0, 0}}}}, 0, 0 }, + { "vnxu", 90, {0, {{{0, 0}}}}, 0, 0 }, + { "cvnxu", 91, {0, {{{0, 0}}}}, 0, 0 }, + { "znxu", 92, {0, {{{0, 0}}}}, 0, 0 }, + { "cznxu", 93, {0, {{{0, 0}}}}, 0, 0 }, + { "vznxu", 94, {0, {{{0, 0}}}}, 0, 0 }, + { "cvznxu", 95, {0, {{{0, 0}}}}, 0, 0 }, + { "iu", 96, {0, {{{0, 0}}}}, 0, 0 }, + { "ciu", 97, {0, {{{0, 0}}}}, 0, 0 }, + { "viu", 98, {0, {{{0, 0}}}}, 0, 0 }, + { "cviu", 99, {0, {{{0, 0}}}}, 0, 0 }, + { "ziu", 100, {0, {{{0, 0}}}}, 0, 0 }, + { "cziu", 101, {0, {{{0, 0}}}}, 0, 0 }, + { "vziu", 102, {0, {{{0, 0}}}}, 0, 0 }, + { "cvziu", 103, {0, {{{0, 0}}}}, 0, 0 }, + { "niu", 104, {0, {{{0, 0}}}}, 0, 0 }, + { "cniu", 105, {0, {{{0, 0}}}}, 0, 0 }, + { "vniu", 106, {0, {{{0, 0}}}}, 0, 0 }, + { "cvniu", 107, {0, {{{0, 0}}}}, 0, 0 }, + { "zniu", 108, {0, {{{0, 0}}}}, 0, 0 }, + { "czniu", 109, {0, {{{0, 0}}}}, 0, 0 }, + { "vzniu", 110, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzniu", 111, {0, {{{0, 0}}}}, 0, 0 }, + { "xiu", 112, {0, {{{0, 0}}}}, 0, 0 }, + { "cxiu", 113, {0, {{{0, 0}}}}, 0, 0 }, + { "vxiu", 114, {0, {{{0, 0}}}}, 0, 0 }, + { "cvxiu", 115, {0, {{{0, 0}}}}, 0, 0 }, + { "zxiu", 116, {0, {{{0, 0}}}}, 0, 0 }, + { "czxiu", 117, {0, {{{0, 0}}}}, 0, 0 }, + { "vzxiu", 118, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzxiu", 119, {0, {{{0, 0}}}}, 0, 0 }, + { "nxiu", 120, {0, {{{0, 0}}}}, 0, 0 }, + { "cnxiu", 121, {0, {{{0, 0}}}}, 0, 0 }, + { "vnxiu", 122, {0, {{{0, 0}}}}, 0, 0 }, + { "cvnxiu", 123, {0, {{{0, 0}}}}, 0, 0 }, + { "znxiu", 124, {0, {{{0, 0}}}}, 0, 0 }, + { "cznxiu", 125, {0, {{{0, 0}}}}, 0, 0 }, + { "vznxiu", 126, {0, {{{0, 0}}}}, 0, 0 }, + { "cvznxiu", 127, {0, {{{0, 0}}}}, 0, 0 }, + { "p", 128, {0, {{{0, 0}}}}, 0, 0 }, + { "cp", 129, {0, {{{0, 0}}}}, 0, 0 }, + { "vp", 130, {0, {{{0, 0}}}}, 0, 0 }, + { "cvp", 131, {0, {{{0, 0}}}}, 0, 0 }, + { "zp", 132, {0, {{{0, 0}}}}, 0, 0 }, + { "czp", 133, {0, {{{0, 0}}}}, 0, 0 }, + { "vzp", 134, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzp", 135, {0, {{{0, 0}}}}, 0, 0 }, + { "np", 136, {0, {{{0, 0}}}}, 0, 0 }, + { "cnp", 137, {0, {{{0, 0}}}}, 0, 0 }, + { "vnp", 138, {0, {{{0, 0}}}}, 0, 0 }, + { "cvnp", 139, {0, {{{0, 0}}}}, 0, 0 }, + { "znp", 140, {0, {{{0, 0}}}}, 0, 0 }, + { "cznp", 141, {0, {{{0, 0}}}}, 0, 0 }, + { "vznp", 142, {0, {{{0, 0}}}}, 0, 0 }, + { "cvznp", 143, {0, {{{0, 0}}}}, 0, 0 }, + { "xp", 144, {0, {{{0, 0}}}}, 0, 0 }, + { "cxp", 145, {0, {{{0, 0}}}}, 0, 0 }, + { "vxp", 146, {0, {{{0, 0}}}}, 0, 0 }, + { "cvxp", 147, {0, {{{0, 0}}}}, 0, 0 }, + { "zxp", 148, {0, {{{0, 0}}}}, 0, 0 }, + { "czxp", 149, {0, {{{0, 0}}}}, 0, 0 }, + { "vzxp", 150, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzxp", 151, {0, {{{0, 0}}}}, 0, 0 }, + { "nxp", 152, {0, {{{0, 0}}}}, 0, 0 }, + { "cnxp", 153, {0, {{{0, 0}}}}, 0, 0 }, + { "vnxp", 154, {0, {{{0, 0}}}}, 0, 0 }, + { "cvnxp", 155, {0, {{{0, 0}}}}, 0, 0 }, + { "znxp", 156, {0, {{{0, 0}}}}, 0, 0 }, + { "cznxp", 157, {0, {{{0, 0}}}}, 0, 0 }, + { "vznxp", 158, {0, {{{0, 0}}}}, 0, 0 }, + { "cvznxp", 159, {0, {{{0, 0}}}}, 0, 0 }, + { "ip", 160, {0, {{{0, 0}}}}, 0, 0 }, + { "cip", 161, {0, {{{0, 0}}}}, 0, 0 }, + { "vip", 162, {0, {{{0, 0}}}}, 0, 0 }, + { "cvip", 163, {0, {{{0, 0}}}}, 0, 0 }, + { "zip", 164, {0, {{{0, 0}}}}, 0, 0 }, + { "czip", 165, {0, {{{0, 0}}}}, 0, 0 }, + { "vzip", 166, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzip", 167, {0, {{{0, 0}}}}, 0, 0 }, + { "nip", 168, {0, {{{0, 0}}}}, 0, 0 }, + { "cnip", 169, {0, {{{0, 0}}}}, 0, 0 }, + { "vnip", 170, {0, {{{0, 0}}}}, 0, 0 }, + { "cvnip", 171, {0, {{{0, 0}}}}, 0, 0 }, + { "znip", 172, {0, {{{0, 0}}}}, 0, 0 }, + { "cznip", 173, {0, {{{0, 0}}}}, 0, 0 }, + { "vznip", 174, {0, {{{0, 0}}}}, 0, 0 }, + { "cvznip", 175, {0, {{{0, 0}}}}, 0, 0 }, + { "xip", 176, {0, {{{0, 0}}}}, 0, 0 }, + { "cxip", 177, {0, {{{0, 0}}}}, 0, 0 }, + { "vxip", 178, {0, {{{0, 0}}}}, 0, 0 }, + { "cvxip", 179, {0, {{{0, 0}}}}, 0, 0 }, + { "zxip", 180, {0, {{{0, 0}}}}, 0, 0 }, + { "czxip", 181, {0, {{{0, 0}}}}, 0, 0 }, + { "vzxip", 182, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzxip", 183, {0, {{{0, 0}}}}, 0, 0 }, + { "nxip", 184, {0, {{{0, 0}}}}, 0, 0 }, + { "cnxip", 185, {0, {{{0, 0}}}}, 0, 0 }, + { "vnxip", 186, {0, {{{0, 0}}}}, 0, 0 }, + { "cvnxip", 187, {0, {{{0, 0}}}}, 0, 0 }, + { "znxip", 188, {0, {{{0, 0}}}}, 0, 0 }, + { "cznxip", 189, {0, {{{0, 0}}}}, 0, 0 }, + { "vznxip", 190, {0, {{{0, 0}}}}, 0, 0 }, + { "cvznxip", 191, {0, {{{0, 0}}}}, 0, 0 }, + { "up", 192, {0, {{{0, 0}}}}, 0, 0 }, + { "cup", 193, {0, {{{0, 0}}}}, 0, 0 }, + { "vup", 194, {0, {{{0, 0}}}}, 0, 0 }, + { "cvup", 195, {0, {{{0, 0}}}}, 0, 0 }, + { "zup", 196, {0, {{{0, 0}}}}, 0, 0 }, + { "czup", 197, {0, {{{0, 0}}}}, 0, 0 }, + { "vzup", 198, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzup", 199, {0, {{{0, 0}}}}, 0, 0 }, + { "nup", 200, {0, {{{0, 0}}}}, 0, 0 }, + { "cnup", 201, {0, {{{0, 0}}}}, 0, 0 }, + { "vnup", 202, {0, {{{0, 0}}}}, 0, 0 }, + { "cvnup", 203, {0, {{{0, 0}}}}, 0, 0 }, + { "znup", 204, {0, {{{0, 0}}}}, 0, 0 }, + { "cznup", 205, {0, {{{0, 0}}}}, 0, 0 }, + { "vznup", 206, {0, {{{0, 0}}}}, 0, 0 }, + { "cvznup", 207, {0, {{{0, 0}}}}, 0, 0 }, + { "xup", 208, {0, {{{0, 0}}}}, 0, 0 }, + { "cxup", 209, {0, {{{0, 0}}}}, 0, 0 }, + { "vxup", 210, {0, {{{0, 0}}}}, 0, 0 }, + { "cvxup", 211, {0, {{{0, 0}}}}, 0, 0 }, + { "zxup", 212, {0, {{{0, 0}}}}, 0, 0 }, + { "czxup", 213, {0, {{{0, 0}}}}, 0, 0 }, + { "vzxup", 214, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzxup", 215, {0, {{{0, 0}}}}, 0, 0 }, + { "nxup", 216, {0, {{{0, 0}}}}, 0, 0 }, + { "cnxup", 217, {0, {{{0, 0}}}}, 0, 0 }, + { "vnxup", 218, {0, {{{0, 0}}}}, 0, 0 }, + { "cvnxup", 219, {0, {{{0, 0}}}}, 0, 0 }, + { "znxup", 220, {0, {{{0, 0}}}}, 0, 0 }, + { "cznxup", 221, {0, {{{0, 0}}}}, 0, 0 }, + { "vznxup", 222, {0, {{{0, 0}}}}, 0, 0 }, + { "cvznxup", 223, {0, {{{0, 0}}}}, 0, 0 }, + { "iup", 224, {0, {{{0, 0}}}}, 0, 0 }, + { "ciup", 225, {0, {{{0, 0}}}}, 0, 0 }, + { "viup", 226, {0, {{{0, 0}}}}, 0, 0 }, + { "cviup", 227, {0, {{{0, 0}}}}, 0, 0 }, + { "ziup", 228, {0, {{{0, 0}}}}, 0, 0 }, + { "cziup", 229, {0, {{{0, 0}}}}, 0, 0 }, + { "vziup", 230, {0, {{{0, 0}}}}, 0, 0 }, + { "cvziup", 231, {0, {{{0, 0}}}}, 0, 0 }, + { "niup", 232, {0, {{{0, 0}}}}, 0, 0 }, + { "cniup", 233, {0, {{{0, 0}}}}, 0, 0 }, + { "vniup", 234, {0, {{{0, 0}}}}, 0, 0 }, + { "cvniup", 235, {0, {{{0, 0}}}}, 0, 0 }, + { "zniup", 236, {0, {{{0, 0}}}}, 0, 0 }, + { "czniup", 237, {0, {{{0, 0}}}}, 0, 0 }, + { "vzniup", 238, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzniup", 239, {0, {{{0, 0}}}}, 0, 0 }, + { "xiup", 240, {0, {{{0, 0}}}}, 0, 0 }, + { "cxiup", 241, {0, {{{0, 0}}}}, 0, 0 }, + { "vxiup", 242, {0, {{{0, 0}}}}, 0, 0 }, + { "cvxiup", 243, {0, {{{0, 0}}}}, 0, 0 }, + { "zxiup", 244, {0, {{{0, 0}}}}, 0, 0 }, + { "czxiup", 245, {0, {{{0, 0}}}}, 0, 0 }, + { "vzxiup", 246, {0, {{{0, 0}}}}, 0, 0 }, + { "cvzxiup", 247, {0, {{{0, 0}}}}, 0, 0 }, + { "nxiup", 248, {0, {{{0, 0}}}}, 0, 0 }, + { "cnxiup", 249, {0, {{{0, 0}}}}, 0, 0 }, + { "vnxiup", 250, {0, {{{0, 0}}}}, 0, 0 }, + { "cvnxiup", 251, {0, {{{0, 0}}}}, 0, 0 }, + { "znxiup", 252, {0, {{{0, 0}}}}, 0, 0 }, + { "cznxiup", 253, {0, {{{0, 0}}}}, 0, 0 }, + { "vznxiup", 254, {0, {{{0, 0}}}}, 0, 0 }, + { "cvznxiup", 255, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD cris_cgen_opval_h_flagbits = +{ + & cris_cgen_opval_h_flagbits_entries[0], + 256, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_supr_entries[] = +{ + { "S0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "S1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "S2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "S3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "S4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "S5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "S6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "S7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "S8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "S9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "S10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "S11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "S12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "S13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "S14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "S15", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD cris_cgen_opval_h_supr = +{ + & cris_cgen_opval_h_supr_entries[0], + 16, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#define A(a) (1 << CGEN_HW_##a) + +const CGEN_HW_ENTRY cris_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of cris_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & cris_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of cris_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & cris_cgen_ifld_table[0]; +} + +/* Subroutine of cris_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & cris_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of cris_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & cris_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of cris_cgen_cpu_open to rebuild the tables. */ + +static void +cris_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & cris_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & cris_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "cris_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + +CGEN_CPU_DESC +cris_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (cris_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "cris_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "cris_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = cris_cgen_rebuild_tables; + cris_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to cris_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +cris_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return cris_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +cris_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/opcodes/cris-desc.h b/opcodes/cris-desc.h new file mode 100644 index 00000000000..0a75b24e806 --- /dev/null +++ b/opcodes/cris-desc.h @@ -0,0 +1,390 @@ +/* CPU data header for cris. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2021 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, see . + +*/ + +#ifndef CRIS_CPU_H +#define CRIS_CPU_H + +#define CGEN_ARCH cris + +/* Given symbol S, return cris_cgen_. */ +#define CGEN_SYM(s) cris##_cgen_##s + + +/* Selected cpu families. */ +#define HAVE_CPU_CRISV0F +#define HAVE_CPU_CRISV3F +#define HAVE_CPU_CRISV8F +#define HAVE_CPU_CRISV10F +#define HAVE_CPU_CRISV32F + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 2 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 6 + +#define CGEN_INT_INSN_P 0 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 6 + +/* Enums. */ + +/* Enum declaration for . */ +typedef enum gr_names_pcreg { + H_GR_REAL_PC_PC = 15, H_GR_REAL_PC_SP = 14, H_GR_REAL_PC_R0 = 0, H_GR_REAL_PC_R1 = 1 + , H_GR_REAL_PC_R2 = 2, H_GR_REAL_PC_R3 = 3, H_GR_REAL_PC_R4 = 4, H_GR_REAL_PC_R5 = 5 + , H_GR_REAL_PC_R6 = 6, H_GR_REAL_PC_R7 = 7, H_GR_REAL_PC_R8 = 8, H_GR_REAL_PC_R9 = 9 + , H_GR_REAL_PC_R10 = 10, H_GR_REAL_PC_R11 = 11, H_GR_REAL_PC_R12 = 12, H_GR_REAL_PC_R13 = 13 + , H_GR_REAL_PC_R14 = 14 +} GR_NAMES_PCREG; + +/* Enum declaration for . */ +typedef enum gr_names_acr { + H_GR_ACR = 15, H_GR_SP = 14, H_GR_R0 = 0, H_GR_R1 = 1 + , H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5 + , H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9 + , H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13 + , H_GR_R14 = 14 +} GR_NAMES_ACR; + +/* Enum declaration for . */ +typedef enum gr_names_v32 { + H_GR_V32_ACR = 15, H_GR_V32_SP = 14, H_GR_V32_R0 = 0, H_GR_V32_R1 = 1 + , H_GR_V32_R2 = 2, H_GR_V32_R3 = 3, H_GR_V32_R4 = 4, H_GR_V32_R5 = 5 + , H_GR_V32_R6 = 6, H_GR_V32_R7 = 7, H_GR_V32_R8 = 8, H_GR_V32_R9 = 9 + , H_GR_V32_R10 = 10, H_GR_V32_R11 = 11, H_GR_V32_R12 = 12, H_GR_V32_R13 = 13 + , H_GR_V32_R14 = 14 +} GR_NAMES_V32; + +/* Enum declaration for . */ +typedef enum p_names_v10 { + H_SR_PRE_V32_CCR = 5, H_SR_PRE_V32_MOF = 7, H_SR_PRE_V32_IBR = 9, H_SR_PRE_V32_IRP = 10 + , H_SR_PRE_V32_BAR = 12, H_SR_PRE_V32_DCCR = 13, H_SR_PRE_V32_BRP = 14, H_SR_PRE_V32_USP = 15 + , H_SR_PRE_V32_VR = 1, H_SR_PRE_V32_SRP = 11, H_SR_PRE_V32_P0 = 0, H_SR_PRE_V32_P1 = 1 + , H_SR_PRE_V32_P2 = 2, H_SR_PRE_V32_P3 = 3, H_SR_PRE_V32_P4 = 4, H_SR_PRE_V32_P5 = 5 + , H_SR_PRE_V32_P6 = 6, H_SR_PRE_V32_P7 = 7, H_SR_PRE_V32_P8 = 8, H_SR_PRE_V32_P9 = 9 + , H_SR_PRE_V32_P10 = 10, H_SR_PRE_V32_P11 = 11, H_SR_PRE_V32_P12 = 12, H_SR_PRE_V32_P13 = 13 + , H_SR_PRE_V32_P14 = 14 +} P_NAMES_V10; + +/* Enum declaration for . */ +typedef enum p_names_v32 { + H_SR_BZ = 0, H_SR_PID = 2, H_SR_SRS = 3, H_SR_WZ = 4 + , H_SR_EXS = 5, H_SR_EDA = 6, H_SR_MOF = 7, H_SR_DZ = 8 + , H_SR_EBP = 9, H_SR_ERP = 10, H_SR_NRP = 12, H_SR_CCS = 13 + , H_SR_USP = 14, H_SR_SPC = 15, H_SR_VR = 1, H_SR_SRP = 11 + , H_SR_P0 = 0, H_SR_P1 = 1, H_SR_P2 = 2, H_SR_P3 = 3 + , H_SR_P4 = 4, H_SR_P5 = 5, H_SR_P6 = 6, H_SR_P7 = 7 + , H_SR_P8 = 8, H_SR_P9 = 9, H_SR_P10 = 10, H_SR_P11 = 11 + , H_SR_P12 = 12, H_SR_P13 = 13, H_SR_P14 = 14 +} P_NAMES_V32; + +/* Enum declaration for . */ +typedef enum p_names_v32_x { + H_SR_V32_BZ = 0, H_SR_V32_PID = 2, H_SR_V32_SRS = 3, H_SR_V32_WZ = 4 + , H_SR_V32_EXS = 5, H_SR_V32_EDA = 6, H_SR_V32_MOF = 7, H_SR_V32_DZ = 8 + , H_SR_V32_EBP = 9, H_SR_V32_ERP = 10, H_SR_V32_NRP = 12, H_SR_V32_CCS = 13 + , H_SR_V32_USP = 14, H_SR_V32_SPC = 15, H_SR_V32_VR = 1, H_SR_V32_SRP = 11 + , H_SR_V32_P0 = 0, H_SR_V32_P1 = 1, H_SR_V32_P2 = 2, H_SR_V32_P3 = 3 + , H_SR_V32_P4 = 4, H_SR_V32_P5 = 5, H_SR_V32_P6 = 6, H_SR_V32_P7 = 7 + , H_SR_V32_P8 = 8, H_SR_V32_P9 = 9, H_SR_V32_P10 = 10, H_SR_V32_P11 = 11 + , H_SR_V32_P12 = 12, H_SR_V32_P13 = 13, H_SR_V32_P14 = 14 +} P_NAMES_V32_X; + +/* Enum declaration for Standard instruction operand size. */ +typedef enum insn_size { + SIZE_BYTE, SIZE_WORD, SIZE_DWORD, SIZE_FIXED +} INSN_SIZE; + +/* Enum declaration for Standard instruction addressing modes. */ +typedef enum insn_mode { + MODE_QUICK_IMMEDIATE, MODE_REGISTER, MODE_INDIRECT, MODE_AUTOINCREMENT +} INSN_MODE; + +/* Enum declaration for Whether the operand is indirect. */ +typedef enum insn_memoryness_mode { + MODEMEMP_NO, MODEMEMP_YES +} INSN_MEMORYNESS_MODE; + +/* Enum declaration for Whether the indirect operand is autoincrement. */ +typedef enum insn_memincness_mode { + MODEINCP_NO, MODEINCP_YES +} INSN_MEMINCNESS_MODE; + +/* Enum declaration for Signed instruction operand size. */ +typedef enum insn_signed_size { + SIGNED_UNDEF_SIZE_0, SIGNED_UNDEF_SIZE_1, SIGNED_BYTE, SIGNED_WORD +} INSN_SIGNED_SIZE; + +/* Enum declaration for Unsigned instruction operand size. */ +typedef enum insn_unsigned_size { + UNSIGNED_BYTE, UNSIGNED_WORD, UNSIGNED_UNDEF_SIZE_2, UNSIGNED_UNDEF_SIZE_3 +} INSN_UNSIGNED_SIZE; + +/* Enum declaration for Insns for MODE_QUICK_IMMEDIATE. */ +typedef enum insn_qi_opc { + Q_BCC_0, Q_BCC_1, Q_BCC_2, Q_BCC_3 + , Q_BDAP_0, Q_BDAP_1, Q_BDAP_2, Q_BDAP_3 + , Q_ADDQ, Q_MOVEQ, Q_SUBQ, Q_CMPQ + , Q_ANDQ, Q_ORQ, Q_ASHQ, Q_LSHQ +} INSN_QI_OPC; + +/* Enum declaration for Same as insn-qi-opc, though using only the high two bits of the opcode. */ +typedef enum insn_qihi_opc { + QHI_BCC, QHI_BDAP, QHI_OTHER2, QHI_OTHER3 +} INSN_QIHI_OPC; + +/* Enum declaration for Insns for MODE_REGISTER and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD. */ +typedef enum insn_r_opc { + R_ADDX, R_MOVX, R_SUBX, R_LSL + , R_ADDI, R_BIAP, R_NEG, R_BOUND + , R_ADD, R_MOVE, R_SUB, R_CMP + , R_AND, R_OR, R_ASR, R_LSR +} INSN_R_OPC; + +/* Enum declaration for Insns for MODE_REGISTER and SIZE_FIXED. */ +typedef enum insn_rfix_opc { + RFIX_ADDX, RFIX_MOVX, RFIX_SUBX, RFIX_BTST + , RFIX_SCC, RFIX_ADDC, RFIX_SETF, RFIX_CLEARF + , RFIX_MOVE_R_S, RFIX_MOVE_S_R, RFIX_ABS, RFIX_DSTEP + , RFIX_LZ, RFIX_SWAP, RFIX_XOR, RFIX_MSTEP +} INSN_RFIX_OPC; + +/* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD. */ +typedef enum insn_indir_opc { + INDIR_ADDX, INDIR_MOVX, INDIR_SUBX, INDIR_CMPX + , INDIR_MUL, INDIR_BDAP_M, INDIR_ADDC, INDIR_BOUND + , INDIR_ADD, INDIR_MOVE_M_R, INDIR_SUB, INDIR_CMP + , INDIR_AND, INDIR_OR, INDIR_TEST, INDIR_MOVE_R_M +} INSN_INDIR_OPC; + +/* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and SIZE_FIXED. */ +typedef enum insn_infix_opc { + INFIX_ADDX, INFIX_MOVX, INFIX_SUBX, INFIX_CMPX + , INFIX_JUMP_M, INFIX_DIP, INFIX_JUMP_R, INFIX_BCC_M + , INFIX_MOVE_M_S, INFIX_MOVE_S_M, INFIX_BMOD, INFIX_BSTORE + , INFIX_RBF, INFIX_SBFS, INFIX_MOVEM_M_R, INFIX_MOVEM_R_M +} INSN_INFIX_OPC; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_CRISV0, MACH_CRISV3, MACH_CRISV8 + , MACH_CRISV10, MACH_CRISV32, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_CRIS, ISA_MAX +} ISA_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) + +/* Enum declaration for cris ifield types. */ +typedef enum ifield_type { + CRIS_F_NIL, CRIS_F_ANYOF, CRIS_F_OPERAND1, CRIS_F_SIZE + , CRIS_F_OPCODE, CRIS_F_MODE, CRIS_F_OPERAND2, CRIS_F_MEMMODE + , CRIS_F_MEMBIT, CRIS_F_B5, CRIS_F_OPCODE_HI, CRIS_F_DSTSRC + , CRIS_F_U6, CRIS_F_S6, CRIS_F_U5, CRIS_F_U4 + , CRIS_F_S8, CRIS_F_DISP9_HI, CRIS_F_DISP9_LO, CRIS_F_DISP9 + , CRIS_F_QO, CRIS_F_INDIR_PC__BYTE, CRIS_F_INDIR_PC__WORD, CRIS_F_INDIR_PC__WORD_PCREL + , CRIS_F_INDIR_PC__DWORD, CRIS_F_INDIR_PC__DWORD_PCREL, CRIS_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) CRIS_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) + +/* Enum declaration for cris hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_INC, HW_H_CCODE, HW_H_SWAP + , HW_H_FLAGBITS, HW_H_V32, HW_H_PC, HW_H_GR + , HW_H_GR_X, HW_H_GR_REAL_PC, HW_H_RAW_GR, HW_H_SR + , HW_H_SR_X, HW_H_SUPR, HW_H_CBIT, HW_H_CBIT_MOVE + , HW_H_CBIT_MOVE_X, HW_H_VBIT, HW_H_VBIT_MOVE, HW_H_VBIT_MOVE_X + , HW_H_ZBIT, HW_H_ZBIT_MOVE, HW_H_ZBIT_MOVE_X, HW_H_NBIT + , HW_H_NBIT_MOVE, HW_H_NBIT_MOVE_X, HW_H_XBIT, HW_H_IBIT + , HW_H_IBIT_X, HW_H_PBIT, HW_H_RBIT, HW_H_UBIT + , HW_H_UBIT_X, HW_H_GBIT, HW_H_KERNEL_SP, HW_H_MBIT + , HW_H_QBIT, HW_H_SBIT, HW_H_INSN_PREFIXED_P, HW_H_INSN_PREFIXED_P_X + , HW_H_PREFIXREG, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + +/* Enum declaration for cris operand types. */ +typedef enum cgen_operand_type { + CRIS_OPERAND_PC, CRIS_OPERAND_CBIT, CRIS_OPERAND_CBIT_MOVE, CRIS_OPERAND_VBIT + , CRIS_OPERAND_VBIT_MOVE, CRIS_OPERAND_ZBIT, CRIS_OPERAND_ZBIT_MOVE, CRIS_OPERAND_NBIT + , CRIS_OPERAND_NBIT_MOVE, CRIS_OPERAND_XBIT, CRIS_OPERAND_IBIT, CRIS_OPERAND_UBIT + , CRIS_OPERAND_PBIT, CRIS_OPERAND_RBIT, CRIS_OPERAND_SBIT, CRIS_OPERAND_MBIT + , CRIS_OPERAND_QBIT, CRIS_OPERAND_PREFIX_SET, CRIS_OPERAND_PREFIXREG, CRIS_OPERAND_RS + , CRIS_OPERAND_INC, CRIS_OPERAND_PS, CRIS_OPERAND_SS, CRIS_OPERAND_SD + , CRIS_OPERAND_I, CRIS_OPERAND_J, CRIS_OPERAND_C, CRIS_OPERAND_QO + , CRIS_OPERAND_RD, CRIS_OPERAND_SCONST8, CRIS_OPERAND_UCONST8, CRIS_OPERAND_SCONST16 + , CRIS_OPERAND_UCONST16, CRIS_OPERAND_CONST32, CRIS_OPERAND_CONST32_PCREL, CRIS_OPERAND_PD + , CRIS_OPERAND_O, CRIS_OPERAND_O_PCREL, CRIS_OPERAND_O_WORD_PCREL, CRIS_OPERAND_CC + , CRIS_OPERAND_N, CRIS_OPERAND_SWAPOPTION, CRIS_OPERAND_LIST_OF_FLAGS, CRIS_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 43 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 + , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld cris_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE cris_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE cris_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE cris_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE cris_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD cris_cgen_opval_h_inc; +extern CGEN_KEYWORD cris_cgen_opval_h_ccode; +extern CGEN_KEYWORD cris_cgen_opval_h_swap; +extern CGEN_KEYWORD cris_cgen_opval_h_flagbits; +extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg; +extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg; +extern CGEN_KEYWORD cris_cgen_opval_gr_names_acr; +extern CGEN_KEYWORD cris_cgen_opval_p_names_v10; +extern CGEN_KEYWORD cris_cgen_opval_p_names_v10; +extern CGEN_KEYWORD cris_cgen_opval_p_names_v10; +extern CGEN_KEYWORD cris_cgen_opval_p_names_v10; +extern CGEN_KEYWORD cris_cgen_opval_p_names_v32; +extern CGEN_KEYWORD cris_cgen_opval_h_supr; + +extern const CGEN_HW_ENTRY cris_cgen_hw_table[]; + + + +#endif /* CRIS_CPU_H */ diff --git a/opcodes/cris-opc.h b/opcodes/cris-opc.h new file mode 100644 index 00000000000..4e297a672ae --- /dev/null +++ b/opcodes/cris-opc.h @@ -0,0 +1,154 @@ +/* Instruction opcode header for cris. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2021 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, see . + +*/ + +#ifndef CRIS_OPC_H +#define CRIS_OPC_H + +/* Enum declaration for cris instruction types. */ +typedef enum cgen_insn_type { + CRIS_INSN_INVALID, CRIS_INSN_NOP, CRIS_INSN_MOVE_B_R, CRIS_INSN_MOVE_W_R + , CRIS_INSN_MOVE_D_R, CRIS_INSN_MOVEPCR, CRIS_INSN_MOVEQ, CRIS_INSN_MOVS_B_R + , CRIS_INSN_MOVS_W_R, CRIS_INSN_MOVU_B_R, CRIS_INSN_MOVU_W_R, CRIS_INSN_MOVECBR + , CRIS_INSN_MOVECWR, CRIS_INSN_MOVECDR, CRIS_INSN_MOVSCBR, CRIS_INSN_MOVSCWR + , CRIS_INSN_MOVUCBR, CRIS_INSN_MOVUCWR, CRIS_INSN_ADDQ, CRIS_INSN_SUBQ + , CRIS_INSN_CMP_R_B_R, CRIS_INSN_CMP_R_W_R, CRIS_INSN_CMP_R_D_R, CRIS_INSN_CMP_M_B_M + , CRIS_INSN_CMP_M_W_M, CRIS_INSN_CMP_M_D_M, CRIS_INSN_CMPCBR, CRIS_INSN_CMPCWR + , CRIS_INSN_CMPCDR, CRIS_INSN_CMPQ, CRIS_INSN_CMPS_M_B_M, CRIS_INSN_CMPS_M_W_M + , CRIS_INSN_CMPSCBR, CRIS_INSN_CMPSCWR, CRIS_INSN_CMPU_M_B_M, CRIS_INSN_CMPU_M_W_M + , CRIS_INSN_CMPUCBR, CRIS_INSN_CMPUCWR, CRIS_INSN_MOVE_M_B_M, CRIS_INSN_MOVE_M_W_M + , CRIS_INSN_MOVE_M_D_M, CRIS_INSN_MOVS_M_B_M, CRIS_INSN_MOVS_M_W_M, CRIS_INSN_MOVU_M_B_M + , CRIS_INSN_MOVU_M_W_M, CRIS_INSN_MOVE_R_SPRV0, CRIS_INSN_MOVE_R_SPRV3, CRIS_INSN_MOVE_R_SPRV8 + , CRIS_INSN_MOVE_R_SPRV10, CRIS_INSN_MOVE_R_SPRV32, CRIS_INSN_MOVE_SPR_RV0, CRIS_INSN_MOVE_SPR_RV3 + , CRIS_INSN_MOVE_SPR_RV8, CRIS_INSN_MOVE_SPR_RV10, CRIS_INSN_MOVE_SPR_RV32, CRIS_INSN_RET_TYPE + , CRIS_INSN_MOVE_M_SPRV0, CRIS_INSN_MOVE_M_SPRV3, CRIS_INSN_MOVE_M_SPRV8, CRIS_INSN_MOVE_M_SPRV10 + , CRIS_INSN_MOVE_M_SPRV32, CRIS_INSN_MOVE_C_SPRV0_P5, CRIS_INSN_MOVE_C_SPRV0_P9, CRIS_INSN_MOVE_C_SPRV0_P10 + , CRIS_INSN_MOVE_C_SPRV0_P11, CRIS_INSN_MOVE_C_SPRV0_P12, CRIS_INSN_MOVE_C_SPRV0_P13, CRIS_INSN_MOVE_C_SPRV0_P6 + , CRIS_INSN_MOVE_C_SPRV0_P7, CRIS_INSN_MOVE_C_SPRV3_P5, CRIS_INSN_MOVE_C_SPRV3_P9, CRIS_INSN_MOVE_C_SPRV3_P10 + , CRIS_INSN_MOVE_C_SPRV3_P11, CRIS_INSN_MOVE_C_SPRV3_P12, CRIS_INSN_MOVE_C_SPRV3_P13, CRIS_INSN_MOVE_C_SPRV3_P6 + , CRIS_INSN_MOVE_C_SPRV3_P7, CRIS_INSN_MOVE_C_SPRV3_P14, CRIS_INSN_MOVE_C_SPRV8_P5, CRIS_INSN_MOVE_C_SPRV8_P9 + , CRIS_INSN_MOVE_C_SPRV8_P10, CRIS_INSN_MOVE_C_SPRV8_P11, CRIS_INSN_MOVE_C_SPRV8_P12, CRIS_INSN_MOVE_C_SPRV8_P13 + , CRIS_INSN_MOVE_C_SPRV8_P14, CRIS_INSN_MOVE_C_SPRV10_P5, CRIS_INSN_MOVE_C_SPRV10_P9, CRIS_INSN_MOVE_C_SPRV10_P10 + , CRIS_INSN_MOVE_C_SPRV10_P11, CRIS_INSN_MOVE_C_SPRV10_P12, CRIS_INSN_MOVE_C_SPRV10_P13, CRIS_INSN_MOVE_C_SPRV10_P7 + , CRIS_INSN_MOVE_C_SPRV10_P14, CRIS_INSN_MOVE_C_SPRV10_P15, CRIS_INSN_MOVE_C_SPRV32_P2, CRIS_INSN_MOVE_C_SPRV32_P3 + , CRIS_INSN_MOVE_C_SPRV32_P5, CRIS_INSN_MOVE_C_SPRV32_P6, CRIS_INSN_MOVE_C_SPRV32_P7, CRIS_INSN_MOVE_C_SPRV32_P9 + , CRIS_INSN_MOVE_C_SPRV32_P10, CRIS_INSN_MOVE_C_SPRV32_P11, CRIS_INSN_MOVE_C_SPRV32_P12, CRIS_INSN_MOVE_C_SPRV32_P13 + , CRIS_INSN_MOVE_C_SPRV32_P14, CRIS_INSN_MOVE_C_SPRV32_P15, CRIS_INSN_MOVE_SPR_MV0, CRIS_INSN_MOVE_SPR_MV3 + , CRIS_INSN_MOVE_SPR_MV8, CRIS_INSN_MOVE_SPR_MV10, CRIS_INSN_MOVE_SPR_MV32, CRIS_INSN_SBFS + , CRIS_INSN_MOVE_SS_R, CRIS_INSN_MOVE_R_SS, CRIS_INSN_MOVEM_R_M, CRIS_INSN_MOVEM_R_M_V32 + , CRIS_INSN_MOVEM_M_R, CRIS_INSN_MOVEM_M_PC, CRIS_INSN_MOVEM_M_R_V32, CRIS_INSN_ADD_B_R + , CRIS_INSN_ADD_W_R, CRIS_INSN_ADD_D_R, CRIS_INSN_ADD_M_B_M, CRIS_INSN_ADD_M_W_M + , CRIS_INSN_ADD_M_D_M, CRIS_INSN_ADDCBR, CRIS_INSN_ADDCWR, CRIS_INSN_ADDCDR + , CRIS_INSN_ADDCPC, CRIS_INSN_ADDS_B_R, CRIS_INSN_ADDS_W_R, CRIS_INSN_ADDS_M_B_M + , CRIS_INSN_ADDS_M_W_M, CRIS_INSN_ADDSCBR, CRIS_INSN_ADDSCWR, CRIS_INSN_ADDSPCPC + , CRIS_INSN_ADDU_B_R, CRIS_INSN_ADDU_W_R, CRIS_INSN_ADDU_M_B_M, CRIS_INSN_ADDU_M_W_M + , CRIS_INSN_ADDUCBR, CRIS_INSN_ADDUCWR, CRIS_INSN_SUB_B_R, CRIS_INSN_SUB_W_R + , CRIS_INSN_SUB_D_R, CRIS_INSN_SUB_M_B_M, CRIS_INSN_SUB_M_W_M, CRIS_INSN_SUB_M_D_M + , CRIS_INSN_SUBCBR, CRIS_INSN_SUBCWR, CRIS_INSN_SUBCDR, CRIS_INSN_SUBS_B_R + , CRIS_INSN_SUBS_W_R, CRIS_INSN_SUBS_M_B_M, CRIS_INSN_SUBS_M_W_M, CRIS_INSN_SUBSCBR + , CRIS_INSN_SUBSCWR, CRIS_INSN_SUBU_B_R, CRIS_INSN_SUBU_W_R, CRIS_INSN_SUBU_M_B_M + , CRIS_INSN_SUBU_M_W_M, CRIS_INSN_SUBUCBR, CRIS_INSN_SUBUCWR, CRIS_INSN_ADDC_R + , CRIS_INSN_ADDC_M, CRIS_INSN_ADDC_C, CRIS_INSN_LAPC_D, CRIS_INSN_LAPCQ + , CRIS_INSN_ADDI_B_R, CRIS_INSN_ADDI_W_R, CRIS_INSN_ADDI_D_R, CRIS_INSN_NEG_B_R + , CRIS_INSN_NEG_W_R, CRIS_INSN_NEG_D_R, CRIS_INSN_TEST_M_B_M, CRIS_INSN_TEST_M_W_M + , CRIS_INSN_TEST_M_D_M, CRIS_INSN_MOVE_R_M_B_M, CRIS_INSN_MOVE_R_M_W_M, CRIS_INSN_MOVE_R_M_D_M + , CRIS_INSN_MULS_B, CRIS_INSN_MULS_W, CRIS_INSN_MULS_D, CRIS_INSN_MULU_B + , CRIS_INSN_MULU_W, CRIS_INSN_MULU_D, CRIS_INSN_MCP, CRIS_INSN_MSTEP + , CRIS_INSN_DSTEP, CRIS_INSN_ABS, CRIS_INSN_AND_B_R, CRIS_INSN_AND_W_R + , CRIS_INSN_AND_D_R, CRIS_INSN_AND_M_B_M, CRIS_INSN_AND_M_W_M, CRIS_INSN_AND_M_D_M + , CRIS_INSN_ANDCBR, CRIS_INSN_ANDCWR, CRIS_INSN_ANDCDR, CRIS_INSN_ANDQ + , CRIS_INSN_ORR_B_R, CRIS_INSN_ORR_W_R, CRIS_INSN_ORR_D_R, CRIS_INSN_OR_M_B_M + , CRIS_INSN_OR_M_W_M, CRIS_INSN_OR_M_D_M, CRIS_INSN_ORCBR, CRIS_INSN_ORCWR + , CRIS_INSN_ORCDR, CRIS_INSN_ORQ, CRIS_INSN_XOR, CRIS_INSN_NOT + , CRIS_INSN_SWAP, CRIS_INSN_ASRR_B_R, CRIS_INSN_ASRR_W_R, CRIS_INSN_ASRR_D_R + , CRIS_INSN_ASRQ, CRIS_INSN_LSRR_B_R, CRIS_INSN_LSRR_W_R, CRIS_INSN_LSRR_D_R + , CRIS_INSN_LSRQ, CRIS_INSN_LSLR_B_R, CRIS_INSN_LSLR_W_R, CRIS_INSN_LSLR_D_R + , CRIS_INSN_LSLQ, CRIS_INSN_BTST, CRIS_INSN_BTSTQ, CRIS_INSN_SETF + , CRIS_INSN_CLEARF, CRIS_INSN_RFE, CRIS_INSN_SFE, CRIS_INSN_RFG + , CRIS_INSN_RFN, CRIS_INSN_HALT, CRIS_INSN_BCC_B, CRIS_INSN_BA_B + , CRIS_INSN_BCC_W, CRIS_INSN_BA_W, CRIS_INSN_JAS_R, CRIS_INSN_JUMP_R + , CRIS_INSN_JAS_C, CRIS_INSN_JUMP_M, CRIS_INSN_JUMP_C, CRIS_INSN_JUMP_P + , CRIS_INSN_BAS_C, CRIS_INSN_JASC_R, CRIS_INSN_JASC_C, CRIS_INSN_BASC_C + , CRIS_INSN_BREAK, CRIS_INSN_BOUND_R_B_R, CRIS_INSN_BOUND_R_W_R, CRIS_INSN_BOUND_R_D_R + , CRIS_INSN_BOUND_M_B_M, CRIS_INSN_BOUND_M_W_M, CRIS_INSN_BOUND_M_D_M, CRIS_INSN_BOUND_CB + , CRIS_INSN_BOUND_CW, CRIS_INSN_BOUND_CD, CRIS_INSN_SCC, CRIS_INSN_LZ + , CRIS_INSN_ADDOQ, CRIS_INSN_BDAPQPC, CRIS_INSN_BDAP_32_PC, CRIS_INSN_MOVE_M_PCPLUS_P0 + , CRIS_INSN_MOVE_M_SPPLUS_P8, CRIS_INSN_ADDO_M_B_M, CRIS_INSN_ADDO_M_W_M, CRIS_INSN_ADDO_M_D_M + , CRIS_INSN_ADDO_CB, CRIS_INSN_ADDO_CW, CRIS_INSN_ADDO_CD, CRIS_INSN_DIP_M + , CRIS_INSN_DIP_C, CRIS_INSN_ADDI_ACR_B_R, CRIS_INSN_ADDI_ACR_W_R, CRIS_INSN_ADDI_ACR_D_R + , CRIS_INSN_BIAP_PC_B_R, CRIS_INSN_BIAP_PC_W_R, CRIS_INSN_BIAP_PC_D_R, CRIS_INSN_FIDXI + , CRIS_INSN_FTAGI, CRIS_INSN_FIDXD, CRIS_INSN_FTAGD +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID CRIS_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) CRIS_INSN_FTAGD + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_operand1; + long f_size; + long f_opcode; + long f_mode; + long f_operand2; + long f_memmode; + long f_membit; + long f_b5; + long f_opcode_hi; + long f_dstsrc; + long f_u6; + long f_s6; + long f_u5; + long f_u4; + long f_s8; + long f_disp9_hi; + long f_disp9_lo; + long f_disp9; + long f_qo; + long f_indir_pc__byte; + long f_indir_pc__word; + long f_indir_pc__word_pcrel; + long f_indir_pc__dword; + long f_indir_pc__dword_pcrel; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* CRIS_OPC_H */ diff --git a/sim/cris/ChangeLog b/sim/cris/ChangeLog index 4e7b919a3c5..5482e083193 100644 --- a/sim/cris/ChangeLog +++ b/sim/cris/ChangeLog @@ -1,3 +1,12 @@ +2021-05-24 Mike Frysinger + + * cris-desc.c, cris-desc.h, cris-opc.h: Moved to opcodes/. + * Makefile.in (SIM_OBJS): Delete cris-desc.o. + (SIM_EXTRA_DEPS): Delete cris-desc.h. + (cris-clean): Delete stamp-desc. + (stamps): Likewise. + (stamp-desc): Delete rule. + 2021-05-23 Mike Frysinger * sim-if.c (sim_open): Delete "x" after PRI macros. diff --git a/sim/cris/Makefile.in b/sim/cris/Makefile.in index 3dcdbb2da02..d5e8a88f3a8 100644 --- a/sim/cris/Makefile.in +++ b/sim/cris/Makefile.in @@ -29,14 +29,13 @@ SIM_OBJS = \ sim-if.o arch.o \ $(CRISV10F_OBJS) \ $(CRISV32F_OBJS) \ - traps.o \ - cris-desc.o + traps.o # Extra headers included by sim-main.h. # FIXME: $(srccom)/cgen-ops.h should be in CGEN_INCLUDE_DEPS. SIM_EXTRA_DEPS = \ $(CGEN_INCLUDE_DEPS) $(srccom)/cgen-ops.h \ - arch.h cpuall.h cris-sim.h cris-desc.h engv10.h engv32.h + arch.h cpuall.h cris-sim.h engv10.h engv32.h SIM_EXTRA_CLEAN = cris-clean @@ -97,7 +96,7 @@ cris-clean: rm -f mloopv$${v}f.c engv$${v}.h stamp-v$${v}fmloop; \ rm -f stamp-v$${v}fcpu; \ done - -rm -f stamp-arch stamp-desc + -rm -f stamp-arch -rm -f tmp-* # cgen support, enable with --enable-cgen-maint @@ -106,7 +105,7 @@ CGEN_MAINT = ; @true @CGEN_MAINT@CGEN_MAINT = # Useful when making CGEN-generated files manually, without --enable-cgen-maint. -stamps: stamp-v10fmloop stamp-v32fmloop stamp-arch stamp-v10fcpu stamp-v32fcpu stamp-desc +stamps: stamp-v10fmloop stamp-v32fmloop stamp-arch stamp-v10fcpu stamp-v32fcpu stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CPU_DIR)/cris.cpu Makefile $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=crisv10,crisv32 \ @@ -135,10 +134,3 @@ stamp-v32fcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CPU_DIR)/cr mv decodev32.c.tmp $(srcdir)/decodev32.c touch stamp-v32fcpu cpuv32.h cpuv32.c semcrisv32f-switch.c modelv32.c decodev32.c decodev32.h: $(CGEN_MAINT) stamp-v32fcpu - -stamp-desc: $(CGEN_READ_SCM) $(CGEN_DESC_SCM) $(CPU_DIR)/cris.cpu Makefile - $(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) \ - archfile=$(CPU_DIR)/cris.cpu \ - cpu=cris mach=all - touch stamp-desc -cris-desc.c cris-desc.h cris-opc.h: $(CGEN_MAINT) stamp-desc diff --git a/sim/cris/cris-desc.c b/sim/cris/cris-desc.c deleted file mode 100644 index 78302e11bbd..00000000000 --- a/sim/cris/cris-desc.c +++ /dev/null @@ -1,2783 +0,0 @@ -/* CPU data for cris. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright 1996-2021 Free Software Foundation, Inc. - -This file is part of the GNU Binutils and/or GDB, the GNU debugger. - - This file is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, see . - -*/ - -#include "sysdep.h" -#include -#include -#include "ansidecl.h" -#include "bfd.h" -#include "symcat.h" -#include "cris-desc.h" -#include "cris-opc.h" -#include "opintl.h" -#include "libiberty.h" -#include "xregex.h" - -/* Attributes. */ - -static const CGEN_ATTR_ENTRY bool_attr[] = -{ - { "#f", 0 }, - { "#t", 1 }, - { 0, 0 } -}; - -static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = -{ - { "base", MACH_BASE }, - { "crisv0", MACH_CRISV0 }, - { "crisv3", MACH_CRISV3 }, - { "crisv8", MACH_CRISV8 }, - { "crisv10", MACH_CRISV10 }, - { "crisv32", MACH_CRISV32 }, - { "max", MACH_MAX }, - { 0, 0 } -}; - -static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = -{ - { "cris", ISA_CRIS }, - { "max", ISA_MAX }, - { 0, 0 } -}; - -const CGEN_ATTR_TABLE cris_cgen_ifield_attr_table[] = -{ - { "MACH", & MACH_attr[0], & MACH_attr[0] }, - { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, - { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, - { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, - { "RESERVED", &bool_attr[0], &bool_attr[0] }, - { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, - { "SIGNED", &bool_attr[0], &bool_attr[0] }, - { 0, 0, 0 } -}; - -const CGEN_ATTR_TABLE cris_cgen_hardware_attr_table[] = -{ - { "MACH", & MACH_attr[0], & MACH_attr[0] }, - { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, - { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, - { "PC", &bool_attr[0], &bool_attr[0] }, - { "PROFILE", &bool_attr[0], &bool_attr[0] }, - { 0, 0, 0 } -}; - -const CGEN_ATTR_TABLE cris_cgen_operand_attr_table[] = -{ - { "MACH", & MACH_attr[0], & MACH_attr[0] }, - { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, - { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, - { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, - { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, - { "SIGNED", &bool_attr[0], &bool_attr[0] }, - { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, - { "RELAX", &bool_attr[0], &bool_attr[0] }, - { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, - { 0, 0, 0 } -}; - -const CGEN_ATTR_TABLE cris_cgen_insn_attr_table[] = -{ - { "MACH", & MACH_attr[0], & MACH_attr[0] }, - { "ALIAS", &bool_attr[0], &bool_attr[0] }, - { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, - { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, - { "COND-CTI", &bool_attr[0], &bool_attr[0] }, - { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, - { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, - { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, - { "RELAXED", &bool_attr[0], &bool_attr[0] }, - { "NO-DIS", &bool_attr[0], &bool_attr[0] }, - { "PBB", &bool_attr[0], &bool_attr[0] }, - { 0, 0, 0 } -}; - -/* Instruction set variants. */ - -static const CGEN_ISA cris_cgen_isa_table[] = { - { "cris", 16, 16, 16, 48 }, - { 0, 0, 0, 0, 0 } -}; - -/* Machine variants. */ - -static const CGEN_MACH cris_cgen_mach_table[] = { - { "crisv0", "cris", MACH_CRISV0, 0 }, - { "crisv3", "cris", MACH_CRISV3, 0 }, - { "crisv8", "cris", MACH_CRISV8, 0 }, - { "crisv10", "cris", MACH_CRISV10, 0 }, - { "crisv32", "crisv32", MACH_CRISV32, 0 }, - { 0, 0, 0, 0 } -}; - -static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_pcreg_entries[] = -{ - { "PC", 15, {0, {{{0, 0}}}}, 0, 0 }, - { "SP", 14, {0, {{{0, 0}}}}, 0, 0 }, - { "R0", 0, {0, {{{0, 0}}}}, 0, 0 }, - { "R1", 1, {0, {{{0, 0}}}}, 0, 0 }, - { "R2", 2, {0, {{{0, 0}}}}, 0, 0 }, - { "R3", 3, {0, {{{0, 0}}}}, 0, 0 }, - { "R4", 4, {0, {{{0, 0}}}}, 0, 0 }, - { "R5", 5, {0, {{{0, 0}}}}, 0, 0 }, - { "R6", 6, {0, {{{0, 0}}}}, 0, 0 }, - { "R7", 7, {0, {{{0, 0}}}}, 0, 0 }, - { "R8", 8, {0, {{{0, 0}}}}, 0, 0 }, - { "R9", 9, {0, {{{0, 0}}}}, 0, 0 }, - { "R10", 10, {0, {{{0, 0}}}}, 0, 0 }, - { "R11", 11, {0, {{{0, 0}}}}, 0, 0 }, - { "R12", 12, {0, {{{0, 0}}}}, 0, 0 }, - { "R13", 13, {0, {{{0, 0}}}}, 0, 0 }, - { "R14", 14, {0, {{{0, 0}}}}, 0, 0 } -}; - -CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg = -{ - & cris_cgen_opval_gr_names_pcreg_entries[0], - 17, - 0, 0, 0, 0, "" -}; - -static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_acr_entries[] = -{ - { "ACR", 15, {0, {{{0, 0}}}}, 0, 0 }, - { "SP", 14, {0, {{{0, 0}}}}, 0, 0 }, - { "R0", 0, {0, {{{0, 0}}}}, 0, 0 }, - { "R1", 1, {0, {{{0, 0}}}}, 0, 0 }, - { "R2", 2, {0, {{{0, 0}}}}, 0, 0 }, - { "R3", 3, {0, {{{0, 0}}}}, 0, 0 }, - { "R4", 4, {0, {{{0, 0}}}}, 0, 0 }, - { "R5", 5, {0, {{{0, 0}}}}, 0, 0 }, - { "R6", 6, {0, {{{0, 0}}}}, 0, 0 }, - { "R7", 7, {0, {{{0, 0}}}}, 0, 0 }, - { "R8", 8, {0, {{{0, 0}}}}, 0, 0 }, - { "R9", 9, {0, {{{0, 0}}}}, 0, 0 }, - { "R10", 10, {0, {{{0, 0}}}}, 0, 0 }, - { "R11", 11, {0, {{{0, 0}}}}, 0, 0 }, - { "R12", 12, {0, {{{0, 0}}}}, 0, 0 }, - { "R13", 13, {0, {{{0, 0}}}}, 0, 0 }, - { "R14", 14, {0, {{{0, 0}}}}, 0, 0 } -}; - -CGEN_KEYWORD cris_cgen_opval_gr_names_acr = -{ - & cris_cgen_opval_gr_names_acr_entries[0], - 17, - 0, 0, 0, 0, "" -}; - -static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_v32_entries[] = -{ - { "ACR", 15, {0, {{{0, 0}}}}, 0, 0 }, - { "SP", 14, {0, {{{0, 0}}}}, 0, 0 }, - { "R0", 0, {0, {{{0, 0}}}}, 0, 0 }, - { "R1", 1, {0, {{{0, 0}}}}, 0, 0 }, - { "R2", 2, {0, {{{0, 0}}}}, 0, 0 }, - { "R3", 3, {0, {{{0, 0}}}}, 0, 0 }, - { "R4", 4, {0, {{{0, 0}}}}, 0, 0 }, - { "R5", 5, {0, {{{0, 0}}}}, 0, 0 }, - { "R6", 6, {0, {{{0, 0}}}}, 0, 0 }, - { "R7", 7, {0, {{{0, 0}}}}, 0, 0 }, - { "R8", 8, {0, {{{0, 0}}}}, 0, 0 }, - { "R9", 9, {0, {{{0, 0}}}}, 0, 0 }, - { "R10", 10, {0, {{{0, 0}}}}, 0, 0 }, - { "R11", 11, {0, {{{0, 0}}}}, 0, 0 }, - { "R12", 12, {0, {{{0, 0}}}}, 0, 0 }, - { "R13", 13, {0, {{{0, 0}}}}, 0, 0 }, - { "R14", 14, {0, {{{0, 0}}}}, 0, 0 } -}; - -CGEN_KEYWORD cris_cgen_opval_gr_names_v32 = -{ - & cris_cgen_opval_gr_names_v32_entries[0], - 17, - 0, 0, 0, 0, "" -}; - -static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v10_entries[] = -{ - { "CCR", 5, {0, {{{0, 0}}}}, 0, 0 }, - { "MOF", 7, {0, {{{0, 0}}}}, 0, 0 }, - { "IBR", 9, {0, {{{0, 0}}}}, 0, 0 }, - { "IRP", 10, {0, {{{0, 0}}}}, 0, 0 }, - { "BAR", 12, {0, {{{0, 0}}}}, 0, 0 }, - { "DCCR", 13, {0, {{{0, 0}}}}, 0, 0 }, - { "BRP", 14, {0, {{{0, 0}}}}, 0, 0 }, - { "USP", 15, {0, {{{0, 0}}}}, 0, 0 }, - { "VR", 1, {0, {{{0, 0}}}}, 0, 0 }, - { "SRP", 11, {0, {{{0, 0}}}}, 0, 0 }, - { "P0", 0, {0, {{{0, 0}}}}, 0, 0 }, - { "P1", 1, {0, {{{0, 0}}}}, 0, 0 }, - { "P2", 2, {0, {{{0, 0}}}}, 0, 0 }, - { "P3", 3, {0, {{{0, 0}}}}, 0, 0 }, - { "P4", 4, {0, {{{0, 0}}}}, 0, 0 }, - { "P5", 5, {0, {{{0, 0}}}}, 0, 0 }, - { "P6", 6, {0, {{{0, 0}}}}, 0, 0 }, - { "P7", 7, {0, {{{0, 0}}}}, 0, 0 }, - { "P8", 8, {0, {{{0, 0}}}}, 0, 0 }, - { "P9", 9, {0, {{{0, 0}}}}, 0, 0 }, - { "P10", 10, {0, {{{0, 0}}}}, 0, 0 }, - { "P11", 11, {0, {{{0, 0}}}}, 0, 0 }, - { "P12", 12, {0, {{{0, 0}}}}, 0, 0 }, - { "P13", 13, {0, {{{0, 0}}}}, 0, 0 }, - { "P14", 14, {0, {{{0, 0}}}}, 0, 0 } -}; - -CGEN_KEYWORD cris_cgen_opval_p_names_v10 = -{ - & cris_cgen_opval_p_names_v10_entries[0], - 25, - 0, 0, 0, 0, "" -}; - -static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v32_entries[] = -{ - { "BZ", 0, {0, {{{0, 0}}}}, 0, 0 }, - { "PID", 2, {0, {{{0, 0}}}}, 0, 0 }, - { "SRS", 3, {0, {{{0, 0}}}}, 0, 0 }, - { "WZ", 4, {0, {{{0, 0}}}}, 0, 0 }, - { "EXS", 5, {0, {{{0, 0}}}}, 0, 0 }, - { "EDA", 6, {0, {{{0, 0}}}}, 0, 0 }, - { "MOF", 7, {0, {{{0, 0}}}}, 0, 0 }, - { "DZ", 8, {0, {{{0, 0}}}}, 0, 0 }, - { "EBP", 9, {0, {{{0, 0}}}}, 0, 0 }, - { "ERP", 10, {0, {{{0, 0}}}}, 0, 0 }, - { "NRP", 12, {0, {{{0, 0}}}}, 0, 0 }, - { "CCS", 13, {0, {{{0, 0}}}}, 0, 0 }, - { "USP", 14, {0, {{{0, 0}}}}, 0, 0 }, - { "SPC", 15, {0, {{{0, 0}}}}, 0, 0 }, - { "VR", 1, {0, {{{0, 0}}}}, 0, 0 }, - { "SRP", 11, {0, {{{0, 0}}}}, 0, 0 }, - { "P0", 0, {0, {{{0, 0}}}}, 0, 0 }, - { "P1", 1, {0, {{{0, 0}}}}, 0, 0 }, - { "P2", 2, {0, {{{0, 0}}}}, 0, 0 }, - { "P3", 3, {0, {{{0, 0}}}}, 0, 0 }, - { "P4", 4, {0, {{{0, 0}}}}, 0, 0 }, - { "P5", 5, {0, {{{0, 0}}}}, 0, 0 }, - { "P6", 6, {0, {{{0, 0}}}}, 0, 0 }, - { "P7", 7, {0, {{{0, 0}}}}, 0, 0 }, - { "P8", 8, {0, {{{0, 0}}}}, 0, 0 }, - { "P9", 9, {0, {{{0, 0}}}}, 0, 0 }, - { "P10", 10, {0, {{{0, 0}}}}, 0, 0 }, - { "P11", 11, {0, {{{0, 0}}}}, 0, 0 }, - { "P12", 12, {0, {{{0, 0}}}}, 0, 0 }, - { "P13", 13, {0, {{{0, 0}}}}, 0, 0 }, - { "P14", 14, {0, {{{0, 0}}}}, 0, 0 } -}; - -CGEN_KEYWORD cris_cgen_opval_p_names_v32 = -{ - & cris_cgen_opval_p_names_v32_entries[0], - 31, - 0, 0, 0, 0, "" -}; - -static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v32_x_entries[] = -{ - { "BZ", 0, {0, {{{0, 0}}}}, 0, 0 }, - { "PID", 2, {0, {{{0, 0}}}}, 0, 0 }, - { "SRS", 3, {0, {{{0, 0}}}}, 0, 0 }, - { "WZ", 4, {0, {{{0, 0}}}}, 0, 0 }, - { "EXS", 5, {0, {{{0, 0}}}}, 0, 0 }, - { "EDA", 6, {0, {{{0, 0}}}}, 0, 0 }, - { "MOF", 7, {0, {{{0, 0}}}}, 0, 0 }, - { "DZ", 8, {0, {{{0, 0}}}}, 0, 0 }, - { "EBP", 9, {0, {{{0, 0}}}}, 0, 0 }, - { "ERP", 10, {0, {{{0, 0}}}}, 0, 0 }, - { "NRP", 12, {0, {{{0, 0}}}}, 0, 0 }, - { "CCS", 13, {0, {{{0, 0}}}}, 0, 0 }, - { "USP", 14, {0, {{{0, 0}}}}, 0, 0 }, - { "SPC", 15, {0, {{{0, 0}}}}, 0, 0 }, - { "VR", 1, {0, {{{0, 0}}}}, 0, 0 }, - { "SRP", 11, {0, {{{0, 0}}}}, 0, 0 }, - { "P0", 0, {0, {{{0, 0}}}}, 0, 0 }, - { "P1", 1, {0, {{{0, 0}}}}, 0, 0 }, - { "P2", 2, {0, {{{0, 0}}}}, 0, 0 }, - { "P3", 3, {0, {{{0, 0}}}}, 0, 0 }, - { "P4", 4, {0, {{{0, 0}}}}, 0, 0 }, - { "P5", 5, {0, {{{0, 0}}}}, 0, 0 }, - { "P6", 6, {0, {{{0, 0}}}}, 0, 0 }, - { "P7", 7, {0, {{{0, 0}}}}, 0, 0 }, - { "P8", 8, {0, {{{0, 0}}}}, 0, 0 }, - { "P9", 9, {0, {{{0, 0}}}}, 0, 0 }, - { "P10", 10, {0, {{{0, 0}}}}, 0, 0 }, - { "P11", 11, {0, {{{0, 0}}}}, 0, 0 }, - { "P12", 12, {0, {{{0, 0}}}}, 0, 0 }, - { "P13", 13, {0, {{{0, 0}}}}, 0, 0 }, - { "P14", 14, {0, {{{0, 0}}}}, 0, 0 } -}; - -CGEN_KEYWORD cris_cgen_opval_p_names_v32_x = -{ - & cris_cgen_opval_p_names_v32_x_entries[0], - 31, - 0, 0, 0, 0, "" -}; - -static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_inc_entries[] = -{ - { "", 0, {0, {{{0, 0}}}}, 0, 0 }, - { "+", 1, {0, {{{0, 0}}}}, 0, 0 } -}; - -CGEN_KEYWORD cris_cgen_opval_h_inc = -{ - & cris_cgen_opval_h_inc_entries[0], - 2, - 0, 0, 0, 0, "" -}; - -static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_ccode_entries[] = -{ - { "cc", 0, {0, {{{0, 0}}}}, 0, 0 }, - { "cs", 1, {0, {{{0, 0}}}}, 0, 0 }, - { "ne", 2, {0, {{{0, 0}}}}, 0, 0 }, - { "eq", 3, {0, {{{0, 0}}}}, 0, 0 }, - { "vc", 4, {0, {{{0, 0}}}}, 0, 0 }, - { "vs", 5, {0, {{{0, 0}}}}, 0, 0 }, - { "pl", 6, {0, {{{0, 0}}}}, 0, 0 }, - { "mi", 7, {0, {{{0, 0}}}}, 0, 0 }, - { "ls", 8, {0, {{{0, 0}}}}, 0, 0 }, - { "hi", 9, {0, {{{0, 0}}}}, 0, 0 }, - { "ge", 10, {0, {{{0, 0}}}}, 0, 0 }, - { "lt", 11, {0, {{{0, 0}}}}, 0, 0 }, - { "gt", 12, {0, {{{0, 0}}}}, 0, 0 }, - { "le", 13, {0, {{{0, 0}}}}, 0, 0 }, - { "a", 14, {0, {{{0, 0}}}}, 0, 0 }, - { "wf", 15, {0, {{{0, 0}}}}, 0, 0 } -}; - -CGEN_KEYWORD cris_cgen_opval_h_ccode = -{ - & cris_cgen_opval_h_ccode_entries[0], - 16, - 0, 0, 0, 0, "" -}; - -static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_swap_entries[] = -{ - { " ", 0, {0, {{{0, 0}}}}, 0, 0 }, - { "r", 1, {0, {{{0, 0}}}}, 0, 0 }, - { "b", 2, {0, {{{0, 0}}}}, 0, 0 }, - { "br", 3, {0, {{{0, 0}}}}, 0, 0 }, - { "w", 4, {0, {{{0, 0}}}}, 0, 0 }, - { "wr", 5, {0, {{{0, 0}}}}, 0, 0 }, - { "wb", 6, {0, {{{0, 0}}}}, 0, 0 }, - { "wbr", 7, {0, {{{0, 0}}}}, 0, 0 }, - { "n", 8, {0, {{{0, 0}}}}, 0, 0 }, - { "nr", 9, {0, {{{0, 0}}}}, 0, 0 }, - { "nb", 10, {0, {{{0, 0}}}}, 0, 0 }, - { "nbr", 11, {0, {{{0, 0}}}}, 0, 0 }, - { "nw", 12, {0, {{{0, 0}}}}, 0, 0 }, - { "nwr", 13, {0, {{{0, 0}}}}, 0, 0 }, - { "nwb", 14, {0, {{{0, 0}}}}, 0, 0 }, - { "nwbr", 15, {0, {{{0, 0}}}}, 0, 0 } -}; - -CGEN_KEYWORD cris_cgen_opval_h_swap = -{ - & cris_cgen_opval_h_swap_entries[0], - 16, - 0, 0, 0, 0, "" -}; - -static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_flagbits_entries[] = -{ - { "_", 0, {0, {{{0, 0}}}}, 0, 0 }, - { "c", 1, {0, {{{0, 0}}}}, 0, 0 }, - { "v", 2, {0, {{{0, 0}}}}, 0, 0 }, - { "cv", 3, {0, {{{0, 0}}}}, 0, 0 }, - { "z", 4, {0, {{{0, 0}}}}, 0, 0 }, - { "cz", 5, {0, {{{0, 0}}}}, 0, 0 }, - { "vz", 6, {0, {{{0, 0}}}}, 0, 0 }, - { "cvz", 7, {0, {{{0, 0}}}}, 0, 0 }, - { "n", 8, {0, {{{0, 0}}}}, 0, 0 }, - { "cn", 9, {0, {{{0, 0}}}}, 0, 0 }, - { "vn", 10, {0, {{{0, 0}}}}, 0, 0 }, - { "cvn", 11, {0, {{{0, 0}}}}, 0, 0 }, - { "zn", 12, {0, {{{0, 0}}}}, 0, 0 }, - { "czn", 13, {0, {{{0, 0}}}}, 0, 0 }, - { "vzn", 14, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzn", 15, {0, {{{0, 0}}}}, 0, 0 }, - { "x", 16, {0, {{{0, 0}}}}, 0, 0 }, - { "cx", 17, {0, {{{0, 0}}}}, 0, 0 }, - { "vx", 18, {0, {{{0, 0}}}}, 0, 0 }, - { "cvx", 19, {0, {{{0, 0}}}}, 0, 0 }, - { "zx", 20, {0, {{{0, 0}}}}, 0, 0 }, - { "czx", 21, {0, {{{0, 0}}}}, 0, 0 }, - { "vzx", 22, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzx", 23, {0, {{{0, 0}}}}, 0, 0 }, - { "nx", 24, {0, {{{0, 0}}}}, 0, 0 }, - { "cnx", 25, {0, {{{0, 0}}}}, 0, 0 }, - { "vnx", 26, {0, {{{0, 0}}}}, 0, 0 }, - { "cvnx", 27, {0, {{{0, 0}}}}, 0, 0 }, - { "znx", 28, {0, {{{0, 0}}}}, 0, 0 }, - { "cznx", 29, {0, {{{0, 0}}}}, 0, 0 }, - { "vznx", 30, {0, {{{0, 0}}}}, 0, 0 }, - { "cvznx", 31, {0, {{{0, 0}}}}, 0, 0 }, - { "i", 32, {0, {{{0, 0}}}}, 0, 0 }, - { "ci", 33, {0, {{{0, 0}}}}, 0, 0 }, - { "vi", 34, {0, {{{0, 0}}}}, 0, 0 }, - { "cvi", 35, {0, {{{0, 0}}}}, 0, 0 }, - { "zi", 36, {0, {{{0, 0}}}}, 0, 0 }, - { "czi", 37, {0, {{{0, 0}}}}, 0, 0 }, - { "vzi", 38, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzi", 39, {0, {{{0, 0}}}}, 0, 0 }, - { "ni", 40, {0, {{{0, 0}}}}, 0, 0 }, - { "cni", 41, {0, {{{0, 0}}}}, 0, 0 }, - { "vni", 42, {0, {{{0, 0}}}}, 0, 0 }, - { "cvni", 43, {0, {{{0, 0}}}}, 0, 0 }, - { "zni", 44, {0, {{{0, 0}}}}, 0, 0 }, - { "czni", 45, {0, {{{0, 0}}}}, 0, 0 }, - { "vzni", 46, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzni", 47, {0, {{{0, 0}}}}, 0, 0 }, - { "xi", 48, {0, {{{0, 0}}}}, 0, 0 }, - { "cxi", 49, {0, {{{0, 0}}}}, 0, 0 }, - { "vxi", 50, {0, {{{0, 0}}}}, 0, 0 }, - { "cvxi", 51, {0, {{{0, 0}}}}, 0, 0 }, - { "zxi", 52, {0, {{{0, 0}}}}, 0, 0 }, - { "czxi", 53, {0, {{{0, 0}}}}, 0, 0 }, - { "vzxi", 54, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzxi", 55, {0, {{{0, 0}}}}, 0, 0 }, - { "nxi", 56, {0, {{{0, 0}}}}, 0, 0 }, - { "cnxi", 57, {0, {{{0, 0}}}}, 0, 0 }, - { "vnxi", 58, {0, {{{0, 0}}}}, 0, 0 }, - { "cvnxi", 59, {0, {{{0, 0}}}}, 0, 0 }, - { "znxi", 60, {0, {{{0, 0}}}}, 0, 0 }, - { "cznxi", 61, {0, {{{0, 0}}}}, 0, 0 }, - { "vznxi", 62, {0, {{{0, 0}}}}, 0, 0 }, - { "cvznxi", 63, {0, {{{0, 0}}}}, 0, 0 }, - { "u", 64, {0, {{{0, 0}}}}, 0, 0 }, - { "cu", 65, {0, {{{0, 0}}}}, 0, 0 }, - { "vu", 66, {0, {{{0, 0}}}}, 0, 0 }, - { "cvu", 67, {0, {{{0, 0}}}}, 0, 0 }, - { "zu", 68, {0, {{{0, 0}}}}, 0, 0 }, - { "czu", 69, {0, {{{0, 0}}}}, 0, 0 }, - { "vzu", 70, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzu", 71, {0, {{{0, 0}}}}, 0, 0 }, - { "nu", 72, {0, {{{0, 0}}}}, 0, 0 }, - { "cnu", 73, {0, {{{0, 0}}}}, 0, 0 }, - { "vnu", 74, {0, {{{0, 0}}}}, 0, 0 }, - { "cvnu", 75, {0, {{{0, 0}}}}, 0, 0 }, - { "znu", 76, {0, {{{0, 0}}}}, 0, 0 }, - { "cznu", 77, {0, {{{0, 0}}}}, 0, 0 }, - { "vznu", 78, {0, {{{0, 0}}}}, 0, 0 }, - { "cvznu", 79, {0, {{{0, 0}}}}, 0, 0 }, - { "xu", 80, {0, {{{0, 0}}}}, 0, 0 }, - { "cxu", 81, {0, {{{0, 0}}}}, 0, 0 }, - { "vxu", 82, {0, {{{0, 0}}}}, 0, 0 }, - { "cvxu", 83, {0, {{{0, 0}}}}, 0, 0 }, - { "zxu", 84, {0, {{{0, 0}}}}, 0, 0 }, - { "czxu", 85, {0, {{{0, 0}}}}, 0, 0 }, - { "vzxu", 86, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzxu", 87, {0, {{{0, 0}}}}, 0, 0 }, - { "nxu", 88, {0, {{{0, 0}}}}, 0, 0 }, - { "cnxu", 89, {0, {{{0, 0}}}}, 0, 0 }, - { "vnxu", 90, {0, {{{0, 0}}}}, 0, 0 }, - { "cvnxu", 91, {0, {{{0, 0}}}}, 0, 0 }, - { "znxu", 92, {0, {{{0, 0}}}}, 0, 0 }, - { "cznxu", 93, {0, {{{0, 0}}}}, 0, 0 }, - { "vznxu", 94, {0, {{{0, 0}}}}, 0, 0 }, - { "cvznxu", 95, {0, {{{0, 0}}}}, 0, 0 }, - { "iu", 96, {0, {{{0, 0}}}}, 0, 0 }, - { "ciu", 97, {0, {{{0, 0}}}}, 0, 0 }, - { "viu", 98, {0, {{{0, 0}}}}, 0, 0 }, - { "cviu", 99, {0, {{{0, 0}}}}, 0, 0 }, - { "ziu", 100, {0, {{{0, 0}}}}, 0, 0 }, - { "cziu", 101, {0, {{{0, 0}}}}, 0, 0 }, - { "vziu", 102, {0, {{{0, 0}}}}, 0, 0 }, - { "cvziu", 103, {0, {{{0, 0}}}}, 0, 0 }, - { "niu", 104, {0, {{{0, 0}}}}, 0, 0 }, - { "cniu", 105, {0, {{{0, 0}}}}, 0, 0 }, - { "vniu", 106, {0, {{{0, 0}}}}, 0, 0 }, - { "cvniu", 107, {0, {{{0, 0}}}}, 0, 0 }, - { "zniu", 108, {0, {{{0, 0}}}}, 0, 0 }, - { "czniu", 109, {0, {{{0, 0}}}}, 0, 0 }, - { "vzniu", 110, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzniu", 111, {0, {{{0, 0}}}}, 0, 0 }, - { "xiu", 112, {0, {{{0, 0}}}}, 0, 0 }, - { "cxiu", 113, {0, {{{0, 0}}}}, 0, 0 }, - { "vxiu", 114, {0, {{{0, 0}}}}, 0, 0 }, - { "cvxiu", 115, {0, {{{0, 0}}}}, 0, 0 }, - { "zxiu", 116, {0, {{{0, 0}}}}, 0, 0 }, - { "czxiu", 117, {0, {{{0, 0}}}}, 0, 0 }, - { "vzxiu", 118, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzxiu", 119, {0, {{{0, 0}}}}, 0, 0 }, - { "nxiu", 120, {0, {{{0, 0}}}}, 0, 0 }, - { "cnxiu", 121, {0, {{{0, 0}}}}, 0, 0 }, - { "vnxiu", 122, {0, {{{0, 0}}}}, 0, 0 }, - { "cvnxiu", 123, {0, {{{0, 0}}}}, 0, 0 }, - { "znxiu", 124, {0, {{{0, 0}}}}, 0, 0 }, - { "cznxiu", 125, {0, {{{0, 0}}}}, 0, 0 }, - { "vznxiu", 126, {0, {{{0, 0}}}}, 0, 0 }, - { "cvznxiu", 127, {0, {{{0, 0}}}}, 0, 0 }, - { "p", 128, {0, {{{0, 0}}}}, 0, 0 }, - { "cp", 129, {0, {{{0, 0}}}}, 0, 0 }, - { "vp", 130, {0, {{{0, 0}}}}, 0, 0 }, - { "cvp", 131, {0, {{{0, 0}}}}, 0, 0 }, - { "zp", 132, {0, {{{0, 0}}}}, 0, 0 }, - { "czp", 133, {0, {{{0, 0}}}}, 0, 0 }, - { "vzp", 134, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzp", 135, {0, {{{0, 0}}}}, 0, 0 }, - { "np", 136, {0, {{{0, 0}}}}, 0, 0 }, - { "cnp", 137, {0, {{{0, 0}}}}, 0, 0 }, - { "vnp", 138, {0, {{{0, 0}}}}, 0, 0 }, - { "cvnp", 139, {0, {{{0, 0}}}}, 0, 0 }, - { "znp", 140, {0, {{{0, 0}}}}, 0, 0 }, - { "cznp", 141, {0, {{{0, 0}}}}, 0, 0 }, - { "vznp", 142, {0, {{{0, 0}}}}, 0, 0 }, - { "cvznp", 143, {0, {{{0, 0}}}}, 0, 0 }, - { "xp", 144, {0, {{{0, 0}}}}, 0, 0 }, - { "cxp", 145, {0, {{{0, 0}}}}, 0, 0 }, - { "vxp", 146, {0, {{{0, 0}}}}, 0, 0 }, - { "cvxp", 147, {0, {{{0, 0}}}}, 0, 0 }, - { "zxp", 148, {0, {{{0, 0}}}}, 0, 0 }, - { "czxp", 149, {0, {{{0, 0}}}}, 0, 0 }, - { "vzxp", 150, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzxp", 151, {0, {{{0, 0}}}}, 0, 0 }, - { "nxp", 152, {0, {{{0, 0}}}}, 0, 0 }, - { "cnxp", 153, {0, {{{0, 0}}}}, 0, 0 }, - { "vnxp", 154, {0, {{{0, 0}}}}, 0, 0 }, - { "cvnxp", 155, {0, {{{0, 0}}}}, 0, 0 }, - { "znxp", 156, {0, {{{0, 0}}}}, 0, 0 }, - { "cznxp", 157, {0, {{{0, 0}}}}, 0, 0 }, - { "vznxp", 158, {0, {{{0, 0}}}}, 0, 0 }, - { "cvznxp", 159, {0, {{{0, 0}}}}, 0, 0 }, - { "ip", 160, {0, {{{0, 0}}}}, 0, 0 }, - { "cip", 161, {0, {{{0, 0}}}}, 0, 0 }, - { "vip", 162, {0, {{{0, 0}}}}, 0, 0 }, - { "cvip", 163, {0, {{{0, 0}}}}, 0, 0 }, - { "zip", 164, {0, {{{0, 0}}}}, 0, 0 }, - { "czip", 165, {0, {{{0, 0}}}}, 0, 0 }, - { "vzip", 166, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzip", 167, {0, {{{0, 0}}}}, 0, 0 }, - { "nip", 168, {0, {{{0, 0}}}}, 0, 0 }, - { "cnip", 169, {0, {{{0, 0}}}}, 0, 0 }, - { "vnip", 170, {0, {{{0, 0}}}}, 0, 0 }, - { "cvnip", 171, {0, {{{0, 0}}}}, 0, 0 }, - { "znip", 172, {0, {{{0, 0}}}}, 0, 0 }, - { "cznip", 173, {0, {{{0, 0}}}}, 0, 0 }, - { "vznip", 174, {0, {{{0, 0}}}}, 0, 0 }, - { "cvznip", 175, {0, {{{0, 0}}}}, 0, 0 }, - { "xip", 176, {0, {{{0, 0}}}}, 0, 0 }, - { "cxip", 177, {0, {{{0, 0}}}}, 0, 0 }, - { "vxip", 178, {0, {{{0, 0}}}}, 0, 0 }, - { "cvxip", 179, {0, {{{0, 0}}}}, 0, 0 }, - { "zxip", 180, {0, {{{0, 0}}}}, 0, 0 }, - { "czxip", 181, {0, {{{0, 0}}}}, 0, 0 }, - { "vzxip", 182, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzxip", 183, {0, {{{0, 0}}}}, 0, 0 }, - { "nxip", 184, {0, {{{0, 0}}}}, 0, 0 }, - { "cnxip", 185, {0, {{{0, 0}}}}, 0, 0 }, - { "vnxip", 186, {0, {{{0, 0}}}}, 0, 0 }, - { "cvnxip", 187, {0, {{{0, 0}}}}, 0, 0 }, - { "znxip", 188, {0, {{{0, 0}}}}, 0, 0 }, - { "cznxip", 189, {0, {{{0, 0}}}}, 0, 0 }, - { "vznxip", 190, {0, {{{0, 0}}}}, 0, 0 }, - { "cvznxip", 191, {0, {{{0, 0}}}}, 0, 0 }, - { "up", 192, {0, {{{0, 0}}}}, 0, 0 }, - { "cup", 193, {0, {{{0, 0}}}}, 0, 0 }, - { "vup", 194, {0, {{{0, 0}}}}, 0, 0 }, - { "cvup", 195, {0, {{{0, 0}}}}, 0, 0 }, - { "zup", 196, {0, {{{0, 0}}}}, 0, 0 }, - { "czup", 197, {0, {{{0, 0}}}}, 0, 0 }, - { "vzup", 198, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzup", 199, {0, {{{0, 0}}}}, 0, 0 }, - { "nup", 200, {0, {{{0, 0}}}}, 0, 0 }, - { "cnup", 201, {0, {{{0, 0}}}}, 0, 0 }, - { "vnup", 202, {0, {{{0, 0}}}}, 0, 0 }, - { "cvnup", 203, {0, {{{0, 0}}}}, 0, 0 }, - { "znup", 204, {0, {{{0, 0}}}}, 0, 0 }, - { "cznup", 205, {0, {{{0, 0}}}}, 0, 0 }, - { "vznup", 206, {0, {{{0, 0}}}}, 0, 0 }, - { "cvznup", 207, {0, {{{0, 0}}}}, 0, 0 }, - { "xup", 208, {0, {{{0, 0}}}}, 0, 0 }, - { "cxup", 209, {0, {{{0, 0}}}}, 0, 0 }, - { "vxup", 210, {0, {{{0, 0}}}}, 0, 0 }, - { "cvxup", 211, {0, {{{0, 0}}}}, 0, 0 }, - { "zxup", 212, {0, {{{0, 0}}}}, 0, 0 }, - { "czxup", 213, {0, {{{0, 0}}}}, 0, 0 }, - { "vzxup", 214, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzxup", 215, {0, {{{0, 0}}}}, 0, 0 }, - { "nxup", 216, {0, {{{0, 0}}}}, 0, 0 }, - { "cnxup", 217, {0, {{{0, 0}}}}, 0, 0 }, - { "vnxup", 218, {0, {{{0, 0}}}}, 0, 0 }, - { "cvnxup", 219, {0, {{{0, 0}}}}, 0, 0 }, - { "znxup", 220, {0, {{{0, 0}}}}, 0, 0 }, - { "cznxup", 221, {0, {{{0, 0}}}}, 0, 0 }, - { "vznxup", 222, {0, {{{0, 0}}}}, 0, 0 }, - { "cvznxup", 223, {0, {{{0, 0}}}}, 0, 0 }, - { "iup", 224, {0, {{{0, 0}}}}, 0, 0 }, - { "ciup", 225, {0, {{{0, 0}}}}, 0, 0 }, - { "viup", 226, {0, {{{0, 0}}}}, 0, 0 }, - { "cviup", 227, {0, {{{0, 0}}}}, 0, 0 }, - { "ziup", 228, {0, {{{0, 0}}}}, 0, 0 }, - { "cziup", 229, {0, {{{0, 0}}}}, 0, 0 }, - { "vziup", 230, {0, {{{0, 0}}}}, 0, 0 }, - { "cvziup", 231, {0, {{{0, 0}}}}, 0, 0 }, - { "niup", 232, {0, {{{0, 0}}}}, 0, 0 }, - { "cniup", 233, {0, {{{0, 0}}}}, 0, 0 }, - { "vniup", 234, {0, {{{0, 0}}}}, 0, 0 }, - { "cvniup", 235, {0, {{{0, 0}}}}, 0, 0 }, - { "zniup", 236, {0, {{{0, 0}}}}, 0, 0 }, - { "czniup", 237, {0, {{{0, 0}}}}, 0, 0 }, - { "vzniup", 238, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzniup", 239, {0, {{{0, 0}}}}, 0, 0 }, - { "xiup", 240, {0, {{{0, 0}}}}, 0, 0 }, - { "cxiup", 241, {0, {{{0, 0}}}}, 0, 0 }, - { "vxiup", 242, {0, {{{0, 0}}}}, 0, 0 }, - { "cvxiup", 243, {0, {{{0, 0}}}}, 0, 0 }, - { "zxiup", 244, {0, {{{0, 0}}}}, 0, 0 }, - { "czxiup", 245, {0, {{{0, 0}}}}, 0, 0 }, - { "vzxiup", 246, {0, {{{0, 0}}}}, 0, 0 }, - { "cvzxiup", 247, {0, {{{0, 0}}}}, 0, 0 }, - { "nxiup", 248, {0, {{{0, 0}}}}, 0, 0 }, - { "cnxiup", 249, {0, {{{0, 0}}}}, 0, 0 }, - { "vnxiup", 250, {0, {{{0, 0}}}}, 0, 0 }, - { "cvnxiup", 251, {0, {{{0, 0}}}}, 0, 0 }, - { "znxiup", 252, {0, {{{0, 0}}}}, 0, 0 }, - { "cznxiup", 253, {0, {{{0, 0}}}}, 0, 0 }, - { "vznxiup", 254, {0, {{{0, 0}}}}, 0, 0 }, - { "cvznxiup", 255, {0, {{{0, 0}}}}, 0, 0 } -}; - -CGEN_KEYWORD cris_cgen_opval_h_flagbits = -{ - & cris_cgen_opval_h_flagbits_entries[0], - 256, - 0, 0, 0, 0, "" -}; - -static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_supr_entries[] = -{ - { "S0", 0, {0, {{{0, 0}}}}, 0, 0 }, - { "S1", 1, {0, {{{0, 0}}}}, 0, 0 }, - { "S2", 2, {0, {{{0, 0}}}}, 0, 0 }, - { "S3", 3, {0, {{{0, 0}}}}, 0, 0 }, - { "S4", 4, {0, {{{0, 0}}}}, 0, 0 }, - { "S5", 5, {0, {{{0, 0}}}}, 0, 0 }, - { "S6", 6, {0, {{{0, 0}}}}, 0, 0 }, - { "S7", 7, {0, {{{0, 0}}}}, 0, 0 }, - { "S8", 8, {0, {{{0, 0}}}}, 0, 0 }, - { "S9", 9, {0, {{{0, 0}}}}, 0, 0 }, - { "S10", 10, {0, {{{0, 0}}}}, 0, 0 }, - { "S11", 11, {0, {{{0, 0}}}}, 0, 0 }, - { "S12", 12, {0, {{{0, 0}}}}, 0, 0 }, - { "S13", 13, {0, {{{0, 0}}}}, 0, 0 }, - { "S14", 14, {0, {{{0, 0}}}}, 0, 0 }, - { "S15", 15, {0, {{{0, 0}}}}, 0, 0 } -}; - -CGEN_KEYWORD cris_cgen_opval_h_supr = -{ - & cris_cgen_opval_h_supr_entries[0], - 16, - 0, 0, 0, 0, "" -}; - - -/* The hardware table. */ - -#define A(a) (1 << CGEN_HW_##a) - -const CGEN_HW_ENTRY cris_cgen_hw_table[] = -{ - { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<name) - { - if (strcmp (name, table->bfd_name) == 0) - return table; - ++table; - } - abort (); -} - -/* Subroutine of cris_cgen_cpu_open to build the hardware table. */ - -static void -build_hw_table (CGEN_CPU_TABLE *cd) -{ - int i; - int machs = cd->machs; - const CGEN_HW_ENTRY *init = & cris_cgen_hw_table[0]; - /* MAX_HW is only an upper bound on the number of selected entries. - However each entry is indexed by it's enum so there can be holes in - the table. */ - const CGEN_HW_ENTRY **selected = - (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); - - cd->hw_table.init_entries = init; - cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); - memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); - /* ??? For now we just use machs to determine which ones we want. */ - for (i = 0; init[i].name != NULL; ++i) - if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) - & machs) - selected[init[i].type] = &init[i]; - cd->hw_table.entries = selected; - cd->hw_table.num_entries = MAX_HW; -} - -/* Subroutine of cris_cgen_cpu_open to build the hardware table. */ - -static void -build_ifield_table (CGEN_CPU_TABLE *cd) -{ - cd->ifld_table = & cris_cgen_ifld_table[0]; -} - -/* Subroutine of cris_cgen_cpu_open to build the hardware table. */ - -static void -build_operand_table (CGEN_CPU_TABLE *cd) -{ - int i; - int machs = cd->machs; - const CGEN_OPERAND *init = & cris_cgen_operand_table[0]; - /* MAX_OPERANDS is only an upper bound on the number of selected entries. - However each entry is indexed by it's enum so there can be holes in - the table. */ - const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); - - cd->operand_table.init_entries = init; - cd->operand_table.entry_size = sizeof (CGEN_OPERAND); - memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); - /* ??? For now we just use mach to determine which ones we want. */ - for (i = 0; init[i].name != NULL; ++i) - if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) - & machs) - selected[init[i].type] = &init[i]; - cd->operand_table.entries = selected; - cd->operand_table.num_entries = MAX_OPERANDS; -} - -/* Subroutine of cris_cgen_cpu_open to build the hardware table. - ??? This could leave out insns not supported by the specified mach/isa, - but that would cause errors like "foo only supported by bar" to become - "unknown insn", so for now we include all insns and require the app to - do the checking later. - ??? On the other hand, parsing of such insns may require their hardware or - operand elements to be in the table [which they mightn't be]. */ - -static void -build_insn_table (CGEN_CPU_TABLE *cd) -{ - int i; - const CGEN_IBASE *ib = & cris_cgen_insn_table[0]; - CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); - - memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); - for (i = 0; i < MAX_INSNS; ++i) - insns[i].base = &ib[i]; - cd->insn_table.init_entries = insns; - cd->insn_table.entry_size = sizeof (CGEN_IBASE); - cd->insn_table.num_init_entries = MAX_INSNS; -} - -/* Subroutine of cris_cgen_cpu_open to rebuild the tables. */ - -static void -cris_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) -{ - int i; - CGEN_BITSET *isas = cd->isas; - unsigned int machs = cd->machs; - - cd->int_insn_p = CGEN_INT_INSN_P; - - /* Data derived from the isa spec. */ -#define UNSET (CGEN_SIZE_UNKNOWN + 1) - cd->default_insn_bitsize = UNSET; - cd->base_insn_bitsize = UNSET; - cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ - cd->max_insn_bitsize = 0; - for (i = 0; i < MAX_ISAS; ++i) - if (cgen_bitset_contains (isas, i)) - { - const CGEN_ISA *isa = & cris_cgen_isa_table[i]; - - /* Default insn sizes of all selected isas must be - equal or we set the result to 0, meaning "unknown". */ - if (cd->default_insn_bitsize == UNSET) - cd->default_insn_bitsize = isa->default_insn_bitsize; - else if (isa->default_insn_bitsize == cd->default_insn_bitsize) - ; /* This is ok. */ - else - cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; - - /* Base insn sizes of all selected isas must be equal - or we set the result to 0, meaning "unknown". */ - if (cd->base_insn_bitsize == UNSET) - cd->base_insn_bitsize = isa->base_insn_bitsize; - else if (isa->base_insn_bitsize == cd->base_insn_bitsize) - ; /* This is ok. */ - else - cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; - - /* Set min,max insn sizes. */ - if (isa->min_insn_bitsize < cd->min_insn_bitsize) - cd->min_insn_bitsize = isa->min_insn_bitsize; - if (isa->max_insn_bitsize > cd->max_insn_bitsize) - cd->max_insn_bitsize = isa->max_insn_bitsize; - } - - /* Data derived from the mach spec. */ - for (i = 0; i < MAX_MACHS; ++i) - if (((1 << i) & machs) != 0) - { - const CGEN_MACH *mach = & cris_cgen_mach_table[i]; - - if (mach->insn_chunk_bitsize != 0) - { - if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) - { - fprintf (stderr, "cris_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", - cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); - abort (); - } - - cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; - } - } - - /* Determine which hw elements are used by MACH. */ - build_hw_table (cd); - - /* Build the ifield table. */ - build_ifield_table (cd); - - /* Determine which operands are used by MACH/ISA. */ - build_operand_table (cd); - - /* Build the instruction table. */ - build_insn_table (cd); -} - -/* Initialize a cpu table and return a descriptor. - It's much like opening a file, and must be the first function called. - The arguments are a set of (type/value) pairs, terminated with - CGEN_CPU_OPEN_END. - - Currently supported values: - CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr - CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr - CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name - CGEN_CPU_OPEN_ENDIAN: specify endian choice - CGEN_CPU_OPEN_END: terminates arguments - - ??? Simultaneous multiple isas might not make sense, but it's not (yet) - precluded. */ - -CGEN_CPU_DESC -cris_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) -{ - CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); - static int init_p; - CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ - unsigned int machs = 0; /* 0 = "unspecified" */ - enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; - va_list ap; - - if (! init_p) - { - init_tables (); - init_p = 1; - } - - memset (cd, 0, sizeof (*cd)); - - va_start (ap, arg_type); - while (arg_type != CGEN_CPU_OPEN_END) - { - switch (arg_type) - { - case CGEN_CPU_OPEN_ISAS : - isas = va_arg (ap, CGEN_BITSET *); - break; - case CGEN_CPU_OPEN_MACHS : - machs = va_arg (ap, unsigned int); - break; - case CGEN_CPU_OPEN_BFDMACH : - { - const char *name = va_arg (ap, const char *); - const CGEN_MACH *mach = - lookup_mach_via_bfd_name (cris_cgen_mach_table, name); - - machs |= 1 << mach->num; - break; - } - case CGEN_CPU_OPEN_ENDIAN : - endian = va_arg (ap, enum cgen_endian); - break; - default : - fprintf (stderr, "cris_cgen_cpu_open: unsupported argument `%d'\n", - arg_type); - abort (); /* ??? return NULL? */ - } - arg_type = va_arg (ap, enum cgen_cpu_open_arg); - } - va_end (ap); - - /* Mach unspecified means "all". */ - if (machs == 0) - machs = (1 << MAX_MACHS) - 1; - /* Base mach is always selected. */ - machs |= 1; - if (endian == CGEN_ENDIAN_UNKNOWN) - { - /* ??? If target has only one, could have a default. */ - fprintf (stderr, "cris_cgen_cpu_open: no endianness specified\n"); - abort (); - } - - cd->isas = cgen_bitset_copy (isas); - cd->machs = machs; - cd->endian = endian; - /* FIXME: for the sparc case we can determine insn-endianness statically. - The worry here is where both data and insn endian can be independently - chosen, in which case this function will need another argument. - Actually, will want to allow for more arguments in the future anyway. */ - cd->insn_endian = endian; - - /* Table (re)builder. */ - cd->rebuild_tables = cris_cgen_rebuild_tables; - cris_cgen_rebuild_tables (cd); - - /* Default to not allowing signed overflow. */ - cd->signed_overflow_ok_p = 0; - - return (CGEN_CPU_DESC) cd; -} - -/* Cover fn to cris_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. - MACH_NAME is the bfd name of the mach. */ - -CGEN_CPU_DESC -cris_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) -{ - return cris_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, - CGEN_CPU_OPEN_ENDIAN, endian, - CGEN_CPU_OPEN_END); -} - -/* Close a cpu table. - ??? This can live in a machine independent file, but there's currently - no place to put this file (there's no libcgen). libopcodes is the wrong - place as some simulator ports use this but they don't use libopcodes. */ - -void -cris_cgen_cpu_close (CGEN_CPU_DESC cd) -{ - unsigned int i; - const CGEN_INSN *insns; - - if (cd->macro_insn_table.init_entries) - { - insns = cd->macro_insn_table.init_entries; - for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) - if (CGEN_INSN_RX ((insns))) - regfree (CGEN_INSN_RX (insns)); - } - - if (cd->insn_table.init_entries) - { - insns = cd->insn_table.init_entries; - for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) - if (CGEN_INSN_RX (insns)) - regfree (CGEN_INSN_RX (insns)); - } - - if (cd->macro_insn_table.init_entries) - free ((CGEN_INSN *) cd->macro_insn_table.init_entries); - - if (cd->insn_table.init_entries) - free ((CGEN_INSN *) cd->insn_table.init_entries); - - if (cd->hw_table.entries) - free ((CGEN_HW_ENTRY *) cd->hw_table.entries); - - if (cd->operand_table.entries) - free ((CGEN_HW_ENTRY *) cd->operand_table.entries); - - free (cd); -} - diff --git a/sim/cris/cris-desc.h b/sim/cris/cris-desc.h deleted file mode 100644 index 0a75b24e806..00000000000 --- a/sim/cris/cris-desc.h +++ /dev/null @@ -1,390 +0,0 @@ -/* CPU data header for cris. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright 1996-2021 Free Software Foundation, Inc. - -This file is part of the GNU Binutils and/or GDB, the GNU debugger. - - This file is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, see . - -*/ - -#ifndef CRIS_CPU_H -#define CRIS_CPU_H - -#define CGEN_ARCH cris - -/* Given symbol S, return cris_cgen_. */ -#define CGEN_SYM(s) cris##_cgen_##s - - -/* Selected cpu families. */ -#define HAVE_CPU_CRISV0F -#define HAVE_CPU_CRISV3F -#define HAVE_CPU_CRISV8F -#define HAVE_CPU_CRISV10F -#define HAVE_CPU_CRISV32F - -#define CGEN_INSN_LSB0_P 1 - -/* Minimum size of any insn (in bytes). */ -#define CGEN_MIN_INSN_SIZE 2 - -/* Maximum size of any insn (in bytes). */ -#define CGEN_MAX_INSN_SIZE 6 - -#define CGEN_INT_INSN_P 0 - -/* Maximum number of syntax elements in an instruction. */ -#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22 - -/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. - e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands - we can't hash on everything up to the space. */ -#define CGEN_MNEMONIC_OPERANDS - -/* Maximum number of fields in an instruction. */ -#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 6 - -/* Enums. */ - -/* Enum declaration for . */ -typedef enum gr_names_pcreg { - H_GR_REAL_PC_PC = 15, H_GR_REAL_PC_SP = 14, H_GR_REAL_PC_R0 = 0, H_GR_REAL_PC_R1 = 1 - , H_GR_REAL_PC_R2 = 2, H_GR_REAL_PC_R3 = 3, H_GR_REAL_PC_R4 = 4, H_GR_REAL_PC_R5 = 5 - , H_GR_REAL_PC_R6 = 6, H_GR_REAL_PC_R7 = 7, H_GR_REAL_PC_R8 = 8, H_GR_REAL_PC_R9 = 9 - , H_GR_REAL_PC_R10 = 10, H_GR_REAL_PC_R11 = 11, H_GR_REAL_PC_R12 = 12, H_GR_REAL_PC_R13 = 13 - , H_GR_REAL_PC_R14 = 14 -} GR_NAMES_PCREG; - -/* Enum declaration for . */ -typedef enum gr_names_acr { - H_GR_ACR = 15, H_GR_SP = 14, H_GR_R0 = 0, H_GR_R1 = 1 - , H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5 - , H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9 - , H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13 - , H_GR_R14 = 14 -} GR_NAMES_ACR; - -/* Enum declaration for . */ -typedef enum gr_names_v32 { - H_GR_V32_ACR = 15, H_GR_V32_SP = 14, H_GR_V32_R0 = 0, H_GR_V32_R1 = 1 - , H_GR_V32_R2 = 2, H_GR_V32_R3 = 3, H_GR_V32_R4 = 4, H_GR_V32_R5 = 5 - , H_GR_V32_R6 = 6, H_GR_V32_R7 = 7, H_GR_V32_R8 = 8, H_GR_V32_R9 = 9 - , H_GR_V32_R10 = 10, H_GR_V32_R11 = 11, H_GR_V32_R12 = 12, H_GR_V32_R13 = 13 - , H_GR_V32_R14 = 14 -} GR_NAMES_V32; - -/* Enum declaration for . */ -typedef enum p_names_v10 { - H_SR_PRE_V32_CCR = 5, H_SR_PRE_V32_MOF = 7, H_SR_PRE_V32_IBR = 9, H_SR_PRE_V32_IRP = 10 - , H_SR_PRE_V32_BAR = 12, H_SR_PRE_V32_DCCR = 13, H_SR_PRE_V32_BRP = 14, H_SR_PRE_V32_USP = 15 - , H_SR_PRE_V32_VR = 1, H_SR_PRE_V32_SRP = 11, H_SR_PRE_V32_P0 = 0, H_SR_PRE_V32_P1 = 1 - , H_SR_PRE_V32_P2 = 2, H_SR_PRE_V32_P3 = 3, H_SR_PRE_V32_P4 = 4, H_SR_PRE_V32_P5 = 5 - , H_SR_PRE_V32_P6 = 6, H_SR_PRE_V32_P7 = 7, H_SR_PRE_V32_P8 = 8, H_SR_PRE_V32_P9 = 9 - , H_SR_PRE_V32_P10 = 10, H_SR_PRE_V32_P11 = 11, H_SR_PRE_V32_P12 = 12, H_SR_PRE_V32_P13 = 13 - , H_SR_PRE_V32_P14 = 14 -} P_NAMES_V10; - -/* Enum declaration for . */ -typedef enum p_names_v32 { - H_SR_BZ = 0, H_SR_PID = 2, H_SR_SRS = 3, H_SR_WZ = 4 - , H_SR_EXS = 5, H_SR_EDA = 6, H_SR_MOF = 7, H_SR_DZ = 8 - , H_SR_EBP = 9, H_SR_ERP = 10, H_SR_NRP = 12, H_SR_CCS = 13 - , H_SR_USP = 14, H_SR_SPC = 15, H_SR_VR = 1, H_SR_SRP = 11 - , H_SR_P0 = 0, H_SR_P1 = 1, H_SR_P2 = 2, H_SR_P3 = 3 - , H_SR_P4 = 4, H_SR_P5 = 5, H_SR_P6 = 6, H_SR_P7 = 7 - , H_SR_P8 = 8, H_SR_P9 = 9, H_SR_P10 = 10, H_SR_P11 = 11 - , H_SR_P12 = 12, H_SR_P13 = 13, H_SR_P14 = 14 -} P_NAMES_V32; - -/* Enum declaration for . */ -typedef enum p_names_v32_x { - H_SR_V32_BZ = 0, H_SR_V32_PID = 2, H_SR_V32_SRS = 3, H_SR_V32_WZ = 4 - , H_SR_V32_EXS = 5, H_SR_V32_EDA = 6, H_SR_V32_MOF = 7, H_SR_V32_DZ = 8 - , H_SR_V32_EBP = 9, H_SR_V32_ERP = 10, H_SR_V32_NRP = 12, H_SR_V32_CCS = 13 - , H_SR_V32_USP = 14, H_SR_V32_SPC = 15, H_SR_V32_VR = 1, H_SR_V32_SRP = 11 - , H_SR_V32_P0 = 0, H_SR_V32_P1 = 1, H_SR_V32_P2 = 2, H_SR_V32_P3 = 3 - , H_SR_V32_P4 = 4, H_SR_V32_P5 = 5, H_SR_V32_P6 = 6, H_SR_V32_P7 = 7 - , H_SR_V32_P8 = 8, H_SR_V32_P9 = 9, H_SR_V32_P10 = 10, H_SR_V32_P11 = 11 - , H_SR_V32_P12 = 12, H_SR_V32_P13 = 13, H_SR_V32_P14 = 14 -} P_NAMES_V32_X; - -/* Enum declaration for Standard instruction operand size. */ -typedef enum insn_size { - SIZE_BYTE, SIZE_WORD, SIZE_DWORD, SIZE_FIXED -} INSN_SIZE; - -/* Enum declaration for Standard instruction addressing modes. */ -typedef enum insn_mode { - MODE_QUICK_IMMEDIATE, MODE_REGISTER, MODE_INDIRECT, MODE_AUTOINCREMENT -} INSN_MODE; - -/* Enum declaration for Whether the operand is indirect. */ -typedef enum insn_memoryness_mode { - MODEMEMP_NO, MODEMEMP_YES -} INSN_MEMORYNESS_MODE; - -/* Enum declaration for Whether the indirect operand is autoincrement. */ -typedef enum insn_memincness_mode { - MODEINCP_NO, MODEINCP_YES -} INSN_MEMINCNESS_MODE; - -/* Enum declaration for Signed instruction operand size. */ -typedef enum insn_signed_size { - SIGNED_UNDEF_SIZE_0, SIGNED_UNDEF_SIZE_1, SIGNED_BYTE, SIGNED_WORD -} INSN_SIGNED_SIZE; - -/* Enum declaration for Unsigned instruction operand size. */ -typedef enum insn_unsigned_size { - UNSIGNED_BYTE, UNSIGNED_WORD, UNSIGNED_UNDEF_SIZE_2, UNSIGNED_UNDEF_SIZE_3 -} INSN_UNSIGNED_SIZE; - -/* Enum declaration for Insns for MODE_QUICK_IMMEDIATE. */ -typedef enum insn_qi_opc { - Q_BCC_0, Q_BCC_1, Q_BCC_2, Q_BCC_3 - , Q_BDAP_0, Q_BDAP_1, Q_BDAP_2, Q_BDAP_3 - , Q_ADDQ, Q_MOVEQ, Q_SUBQ, Q_CMPQ - , Q_ANDQ, Q_ORQ, Q_ASHQ, Q_LSHQ -} INSN_QI_OPC; - -/* Enum declaration for Same as insn-qi-opc, though using only the high two bits of the opcode. */ -typedef enum insn_qihi_opc { - QHI_BCC, QHI_BDAP, QHI_OTHER2, QHI_OTHER3 -} INSN_QIHI_OPC; - -/* Enum declaration for Insns for MODE_REGISTER and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD. */ -typedef enum insn_r_opc { - R_ADDX, R_MOVX, R_SUBX, R_LSL - , R_ADDI, R_BIAP, R_NEG, R_BOUND - , R_ADD, R_MOVE, R_SUB, R_CMP - , R_AND, R_OR, R_ASR, R_LSR -} INSN_R_OPC; - -/* Enum declaration for Insns for MODE_REGISTER and SIZE_FIXED. */ -typedef enum insn_rfix_opc { - RFIX_ADDX, RFIX_MOVX, RFIX_SUBX, RFIX_BTST - , RFIX_SCC, RFIX_ADDC, RFIX_SETF, RFIX_CLEARF - , RFIX_MOVE_R_S, RFIX_MOVE_S_R, RFIX_ABS, RFIX_DSTEP - , RFIX_LZ, RFIX_SWAP, RFIX_XOR, RFIX_MSTEP -} INSN_RFIX_OPC; - -/* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD. */ -typedef enum insn_indir_opc { - INDIR_ADDX, INDIR_MOVX, INDIR_SUBX, INDIR_CMPX - , INDIR_MUL, INDIR_BDAP_M, INDIR_ADDC, INDIR_BOUND - , INDIR_ADD, INDIR_MOVE_M_R, INDIR_SUB, INDIR_CMP - , INDIR_AND, INDIR_OR, INDIR_TEST, INDIR_MOVE_R_M -} INSN_INDIR_OPC; - -/* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and SIZE_FIXED. */ -typedef enum insn_infix_opc { - INFIX_ADDX, INFIX_MOVX, INFIX_SUBX, INFIX_CMPX - , INFIX_JUMP_M, INFIX_DIP, INFIX_JUMP_R, INFIX_BCC_M - , INFIX_MOVE_M_S, INFIX_MOVE_S_M, INFIX_BMOD, INFIX_BSTORE - , INFIX_RBF, INFIX_SBFS, INFIX_MOVEM_M_R, INFIX_MOVEM_R_M -} INSN_INFIX_OPC; - -/* Attributes. */ - -/* Enum declaration for machine type selection. */ -typedef enum mach_attr { - MACH_BASE, MACH_CRISV0, MACH_CRISV3, MACH_CRISV8 - , MACH_CRISV10, MACH_CRISV32, MACH_MAX -} MACH_ATTR; - -/* Enum declaration for instruction set selection. */ -typedef enum isa_attr { - ISA_CRIS, ISA_MAX -} ISA_ATTR; - -/* Number of architecture variants. */ -#define MAX_ISAS 1 -#define MAX_MACHS ((int) MACH_MAX) - -/* Ifield support. */ - -/* Ifield attribute indices. */ - -/* Enum declaration for cgen_ifld attrs. */ -typedef enum cgen_ifld_attr { - CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED - , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 - , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS -} CGEN_IFLD_ATTR; - -/* Number of non-boolean elements in cgen_ifld_attr. */ -#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) - -/* cgen_ifld attribute accessor macros. */ -#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) -#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) -#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) -#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) -#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) -#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) -#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) - -/* Enum declaration for cris ifield types. */ -typedef enum ifield_type { - CRIS_F_NIL, CRIS_F_ANYOF, CRIS_F_OPERAND1, CRIS_F_SIZE - , CRIS_F_OPCODE, CRIS_F_MODE, CRIS_F_OPERAND2, CRIS_F_MEMMODE - , CRIS_F_MEMBIT, CRIS_F_B5, CRIS_F_OPCODE_HI, CRIS_F_DSTSRC - , CRIS_F_U6, CRIS_F_S6, CRIS_F_U5, CRIS_F_U4 - , CRIS_F_S8, CRIS_F_DISP9_HI, CRIS_F_DISP9_LO, CRIS_F_DISP9 - , CRIS_F_QO, CRIS_F_INDIR_PC__BYTE, CRIS_F_INDIR_PC__WORD, CRIS_F_INDIR_PC__WORD_PCREL - , CRIS_F_INDIR_PC__DWORD, CRIS_F_INDIR_PC__DWORD_PCREL, CRIS_F_MAX -} IFIELD_TYPE; - -#define MAX_IFLD ((int) CRIS_F_MAX) - -/* Hardware attribute indices. */ - -/* Enum declaration for cgen_hw attrs. */ -typedef enum cgen_hw_attr { - CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE - , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS -} CGEN_HW_ATTR; - -/* Number of non-boolean elements in cgen_hw_attr. */ -#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) - -/* cgen_hw attribute accessor macros. */ -#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) -#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) -#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) -#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) -#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) - -/* Enum declaration for cris hardware types. */ -typedef enum cgen_hw_type { - HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR - , HW_H_IADDR, HW_H_INC, HW_H_CCODE, HW_H_SWAP - , HW_H_FLAGBITS, HW_H_V32, HW_H_PC, HW_H_GR - , HW_H_GR_X, HW_H_GR_REAL_PC, HW_H_RAW_GR, HW_H_SR - , HW_H_SR_X, HW_H_SUPR, HW_H_CBIT, HW_H_CBIT_MOVE - , HW_H_CBIT_MOVE_X, HW_H_VBIT, HW_H_VBIT_MOVE, HW_H_VBIT_MOVE_X - , HW_H_ZBIT, HW_H_ZBIT_MOVE, HW_H_ZBIT_MOVE_X, HW_H_NBIT - , HW_H_NBIT_MOVE, HW_H_NBIT_MOVE_X, HW_H_XBIT, HW_H_IBIT - , HW_H_IBIT_X, HW_H_PBIT, HW_H_RBIT, HW_H_UBIT - , HW_H_UBIT_X, HW_H_GBIT, HW_H_KERNEL_SP, HW_H_MBIT - , HW_H_QBIT, HW_H_SBIT, HW_H_INSN_PREFIXED_P, HW_H_INSN_PREFIXED_P_X - , HW_H_PREFIXREG, HW_MAX -} CGEN_HW_TYPE; - -#define MAX_HW ((int) HW_MAX) - -/* Operand attribute indices. */ - -/* Enum declaration for cgen_operand attrs. */ -typedef enum cgen_operand_attr { - CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT - , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY - , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS -} CGEN_OPERAND_ATTR; - -/* Number of non-boolean elements in cgen_operand_attr. */ -#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) - -/* cgen_operand attribute accessor macros. */ -#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) -#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) -#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) -#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) -#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) -#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) -#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) -#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) -#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) - -/* Enum declaration for cris operand types. */ -typedef enum cgen_operand_type { - CRIS_OPERAND_PC, CRIS_OPERAND_CBIT, CRIS_OPERAND_CBIT_MOVE, CRIS_OPERAND_VBIT - , CRIS_OPERAND_VBIT_MOVE, CRIS_OPERAND_ZBIT, CRIS_OPERAND_ZBIT_MOVE, CRIS_OPERAND_NBIT - , CRIS_OPERAND_NBIT_MOVE, CRIS_OPERAND_XBIT, CRIS_OPERAND_IBIT, CRIS_OPERAND_UBIT - , CRIS_OPERAND_PBIT, CRIS_OPERAND_RBIT, CRIS_OPERAND_SBIT, CRIS_OPERAND_MBIT - , CRIS_OPERAND_QBIT, CRIS_OPERAND_PREFIX_SET, CRIS_OPERAND_PREFIXREG, CRIS_OPERAND_RS - , CRIS_OPERAND_INC, CRIS_OPERAND_PS, CRIS_OPERAND_SS, CRIS_OPERAND_SD - , CRIS_OPERAND_I, CRIS_OPERAND_J, CRIS_OPERAND_C, CRIS_OPERAND_QO - , CRIS_OPERAND_RD, CRIS_OPERAND_SCONST8, CRIS_OPERAND_UCONST8, CRIS_OPERAND_SCONST16 - , CRIS_OPERAND_UCONST16, CRIS_OPERAND_CONST32, CRIS_OPERAND_CONST32_PCREL, CRIS_OPERAND_PD - , CRIS_OPERAND_O, CRIS_OPERAND_O_PCREL, CRIS_OPERAND_O_WORD_PCREL, CRIS_OPERAND_CC - , CRIS_OPERAND_N, CRIS_OPERAND_SWAPOPTION, CRIS_OPERAND_LIST_OF_FLAGS, CRIS_OPERAND_MAX -} CGEN_OPERAND_TYPE; - -/* Number of operands types. */ -#define MAX_OPERANDS 43 - -/* Maximum number of operands referenced by any insn. */ -#define MAX_OPERAND_INSTANCES 8 - -/* Insn attribute indices. */ - -/* Enum declaration for cgen_insn attrs. */ -typedef enum cgen_insn_attr { - CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI - , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED - , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 - , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS -} CGEN_INSN_ATTR; - -/* Number of non-boolean elements in cgen_insn_attr. */ -#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) - -/* cgen_insn attribute accessor macros. */ -#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) -#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) -#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) -#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) -#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) -#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) -#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) -#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) -#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) -#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) -#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) - -/* cgen.h uses things we just defined. */ -#include "opcode/cgen.h" - -extern const struct cgen_ifld cris_cgen_ifld_table[]; - -/* Attributes. */ -extern const CGEN_ATTR_TABLE cris_cgen_hardware_attr_table[]; -extern const CGEN_ATTR_TABLE cris_cgen_ifield_attr_table[]; -extern const CGEN_ATTR_TABLE cris_cgen_operand_attr_table[]; -extern const CGEN_ATTR_TABLE cris_cgen_insn_attr_table[]; - -/* Hardware decls. */ - -extern CGEN_KEYWORD cris_cgen_opval_h_inc; -extern CGEN_KEYWORD cris_cgen_opval_h_ccode; -extern CGEN_KEYWORD cris_cgen_opval_h_swap; -extern CGEN_KEYWORD cris_cgen_opval_h_flagbits; -extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg; -extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg; -extern CGEN_KEYWORD cris_cgen_opval_gr_names_acr; -extern CGEN_KEYWORD cris_cgen_opval_p_names_v10; -extern CGEN_KEYWORD cris_cgen_opval_p_names_v10; -extern CGEN_KEYWORD cris_cgen_opval_p_names_v10; -extern CGEN_KEYWORD cris_cgen_opval_p_names_v10; -extern CGEN_KEYWORD cris_cgen_opval_p_names_v32; -extern CGEN_KEYWORD cris_cgen_opval_h_supr; - -extern const CGEN_HW_ENTRY cris_cgen_hw_table[]; - - - -#endif /* CRIS_CPU_H */ diff --git a/sim/cris/cris-opc.h b/sim/cris/cris-opc.h deleted file mode 100644 index 4e297a672ae..00000000000 --- a/sim/cris/cris-opc.h +++ /dev/null @@ -1,154 +0,0 @@ -/* Instruction opcode header for cris. - -THIS FILE IS MACHINE GENERATED WITH CGEN. - -Copyright 1996-2021 Free Software Foundation, Inc. - -This file is part of the GNU Binutils and/or GDB, the GNU debugger. - - This file is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, see . - -*/ - -#ifndef CRIS_OPC_H -#define CRIS_OPC_H - -/* Enum declaration for cris instruction types. */ -typedef enum cgen_insn_type { - CRIS_INSN_INVALID, CRIS_INSN_NOP, CRIS_INSN_MOVE_B_R, CRIS_INSN_MOVE_W_R - , CRIS_INSN_MOVE_D_R, CRIS_INSN_MOVEPCR, CRIS_INSN_MOVEQ, CRIS_INSN_MOVS_B_R - , CRIS_INSN_MOVS_W_R, CRIS_INSN_MOVU_B_R, CRIS_INSN_MOVU_W_R, CRIS_INSN_MOVECBR - , CRIS_INSN_MOVECWR, CRIS_INSN_MOVECDR, CRIS_INSN_MOVSCBR, CRIS_INSN_MOVSCWR - , CRIS_INSN_MOVUCBR, CRIS_INSN_MOVUCWR, CRIS_INSN_ADDQ, CRIS_INSN_SUBQ - , CRIS_INSN_CMP_R_B_R, CRIS_INSN_CMP_R_W_R, CRIS_INSN_CMP_R_D_R, CRIS_INSN_CMP_M_B_M - , CRIS_INSN_CMP_M_W_M, CRIS_INSN_CMP_M_D_M, CRIS_INSN_CMPCBR, CRIS_INSN_CMPCWR - , CRIS_INSN_CMPCDR, CRIS_INSN_CMPQ, CRIS_INSN_CMPS_M_B_M, CRIS_INSN_CMPS_M_W_M - , CRIS_INSN_CMPSCBR, CRIS_INSN_CMPSCWR, CRIS_INSN_CMPU_M_B_M, CRIS_INSN_CMPU_M_W_M - , CRIS_INSN_CMPUCBR, CRIS_INSN_CMPUCWR, CRIS_INSN_MOVE_M_B_M, CRIS_INSN_MOVE_M_W_M - , CRIS_INSN_MOVE_M_D_M, CRIS_INSN_MOVS_M_B_M, CRIS_INSN_MOVS_M_W_M, CRIS_INSN_MOVU_M_B_M - , CRIS_INSN_MOVU_M_W_M, CRIS_INSN_MOVE_R_SPRV0, CRIS_INSN_MOVE_R_SPRV3, CRIS_INSN_MOVE_R_SPRV8 - , CRIS_INSN_MOVE_R_SPRV10, CRIS_INSN_MOVE_R_SPRV32, CRIS_INSN_MOVE_SPR_RV0, CRIS_INSN_MOVE_SPR_RV3 - , CRIS_INSN_MOVE_SPR_RV8, CRIS_INSN_MOVE_SPR_RV10, CRIS_INSN_MOVE_SPR_RV32, CRIS_INSN_RET_TYPE - , CRIS_INSN_MOVE_M_SPRV0, CRIS_INSN_MOVE_M_SPRV3, CRIS_INSN_MOVE_M_SPRV8, CRIS_INSN_MOVE_M_SPRV10 - , CRIS_INSN_MOVE_M_SPRV32, CRIS_INSN_MOVE_C_SPRV0_P5, CRIS_INSN_MOVE_C_SPRV0_P9, CRIS_INSN_MOVE_C_SPRV0_P10 - , CRIS_INSN_MOVE_C_SPRV0_P11, CRIS_INSN_MOVE_C_SPRV0_P12, CRIS_INSN_MOVE_C_SPRV0_P13, CRIS_INSN_MOVE_C_SPRV0_P6 - , CRIS_INSN_MOVE_C_SPRV0_P7, CRIS_INSN_MOVE_C_SPRV3_P5, CRIS_INSN_MOVE_C_SPRV3_P9, CRIS_INSN_MOVE_C_SPRV3_P10 - , CRIS_INSN_MOVE_C_SPRV3_P11, CRIS_INSN_MOVE_C_SPRV3_P12, CRIS_INSN_MOVE_C_SPRV3_P13, CRIS_INSN_MOVE_C_SPRV3_P6 - , CRIS_INSN_MOVE_C_SPRV3_P7, CRIS_INSN_MOVE_C_SPRV3_P14, CRIS_INSN_MOVE_C_SPRV8_P5, CRIS_INSN_MOVE_C_SPRV8_P9 - , CRIS_INSN_MOVE_C_SPRV8_P10, CRIS_INSN_MOVE_C_SPRV8_P11, CRIS_INSN_MOVE_C_SPRV8_P12, CRIS_INSN_MOVE_C_SPRV8_P13 - , CRIS_INSN_MOVE_C_SPRV8_P14, CRIS_INSN_MOVE_C_SPRV10_P5, CRIS_INSN_MOVE_C_SPRV10_P9, CRIS_INSN_MOVE_C_SPRV10_P10 - , CRIS_INSN_MOVE_C_SPRV10_P11, CRIS_INSN_MOVE_C_SPRV10_P12, CRIS_INSN_MOVE_C_SPRV10_P13, CRIS_INSN_MOVE_C_SPRV10_P7 - , CRIS_INSN_MOVE_C_SPRV10_P14, CRIS_INSN_MOVE_C_SPRV10_P15, CRIS_INSN_MOVE_C_SPRV32_P2, CRIS_INSN_MOVE_C_SPRV32_P3 - , CRIS_INSN_MOVE_C_SPRV32_P5, CRIS_INSN_MOVE_C_SPRV32_P6, CRIS_INSN_MOVE_C_SPRV32_P7, CRIS_INSN_MOVE_C_SPRV32_P9 - , CRIS_INSN_MOVE_C_SPRV32_P10, CRIS_INSN_MOVE_C_SPRV32_P11, CRIS_INSN_MOVE_C_SPRV32_P12, CRIS_INSN_MOVE_C_SPRV32_P13 - , CRIS_INSN_MOVE_C_SPRV32_P14, CRIS_INSN_MOVE_C_SPRV32_P15, CRIS_INSN_MOVE_SPR_MV0, CRIS_INSN_MOVE_SPR_MV3 - , CRIS_INSN_MOVE_SPR_MV8, CRIS_INSN_MOVE_SPR_MV10, CRIS_INSN_MOVE_SPR_MV32, CRIS_INSN_SBFS - , CRIS_INSN_MOVE_SS_R, CRIS_INSN_MOVE_R_SS, CRIS_INSN_MOVEM_R_M, CRIS_INSN_MOVEM_R_M_V32 - , CRIS_INSN_MOVEM_M_R, CRIS_INSN_MOVEM_M_PC, CRIS_INSN_MOVEM_M_R_V32, CRIS_INSN_ADD_B_R - , CRIS_INSN_ADD_W_R, CRIS_INSN_ADD_D_R, CRIS_INSN_ADD_M_B_M, CRIS_INSN_ADD_M_W_M - , CRIS_INSN_ADD_M_D_M, CRIS_INSN_ADDCBR, CRIS_INSN_ADDCWR, CRIS_INSN_ADDCDR - , CRIS_INSN_ADDCPC, CRIS_INSN_ADDS_B_R, CRIS_INSN_ADDS_W_R, CRIS_INSN_ADDS_M_B_M - , CRIS_INSN_ADDS_M_W_M, CRIS_INSN_ADDSCBR, CRIS_INSN_ADDSCWR, CRIS_INSN_ADDSPCPC - , CRIS_INSN_ADDU_B_R, CRIS_INSN_ADDU_W_R, CRIS_INSN_ADDU_M_B_M, CRIS_INSN_ADDU_M_W_M - , CRIS_INSN_ADDUCBR, CRIS_INSN_ADDUCWR, CRIS_INSN_SUB_B_R, CRIS_INSN_SUB_W_R - , CRIS_INSN_SUB_D_R, CRIS_INSN_SUB_M_B_M, CRIS_INSN_SUB_M_W_M, CRIS_INSN_SUB_M_D_M - , CRIS_INSN_SUBCBR, CRIS_INSN_SUBCWR, CRIS_INSN_SUBCDR, CRIS_INSN_SUBS_B_R - , CRIS_INSN_SUBS_W_R, CRIS_INSN_SUBS_M_B_M, CRIS_INSN_SUBS_M_W_M, CRIS_INSN_SUBSCBR - , CRIS_INSN_SUBSCWR, CRIS_INSN_SUBU_B_R, CRIS_INSN_SUBU_W_R, CRIS_INSN_SUBU_M_B_M - , CRIS_INSN_SUBU_M_W_M, CRIS_INSN_SUBUCBR, CRIS_INSN_SUBUCWR, CRIS_INSN_ADDC_R - , CRIS_INSN_ADDC_M, CRIS_INSN_ADDC_C, CRIS_INSN_LAPC_D, CRIS_INSN_LAPCQ - , CRIS_INSN_ADDI_B_R, CRIS_INSN_ADDI_W_R, CRIS_INSN_ADDI_D_R, CRIS_INSN_NEG_B_R - , CRIS_INSN_NEG_W_R, CRIS_INSN_NEG_D_R, CRIS_INSN_TEST_M_B_M, CRIS_INSN_TEST_M_W_M - , CRIS_INSN_TEST_M_D_M, CRIS_INSN_MOVE_R_M_B_M, CRIS_INSN_MOVE_R_M_W_M, CRIS_INSN_MOVE_R_M_D_M - , CRIS_INSN_MULS_B, CRIS_INSN_MULS_W, CRIS_INSN_MULS_D, CRIS_INSN_MULU_B - , CRIS_INSN_MULU_W, CRIS_INSN_MULU_D, CRIS_INSN_MCP, CRIS_INSN_MSTEP - , CRIS_INSN_DSTEP, CRIS_INSN_ABS, CRIS_INSN_AND_B_R, CRIS_INSN_AND_W_R - , CRIS_INSN_AND_D_R, CRIS_INSN_AND_M_B_M, CRIS_INSN_AND_M_W_M, CRIS_INSN_AND_M_D_M - , CRIS_INSN_ANDCBR, CRIS_INSN_ANDCWR, CRIS_INSN_ANDCDR, CRIS_INSN_ANDQ - , CRIS_INSN_ORR_B_R, CRIS_INSN_ORR_W_R, CRIS_INSN_ORR_D_R, CRIS_INSN_OR_M_B_M - , CRIS_INSN_OR_M_W_M, CRIS_INSN_OR_M_D_M, CRIS_INSN_ORCBR, CRIS_INSN_ORCWR - , CRIS_INSN_ORCDR, CRIS_INSN_ORQ, CRIS_INSN_XOR, CRIS_INSN_NOT - , CRIS_INSN_SWAP, CRIS_INSN_ASRR_B_R, CRIS_INSN_ASRR_W_R, CRIS_INSN_ASRR_D_R - , CRIS_INSN_ASRQ, CRIS_INSN_LSRR_B_R, CRIS_INSN_LSRR_W_R, CRIS_INSN_LSRR_D_R - , CRIS_INSN_LSRQ, CRIS_INSN_LSLR_B_R, CRIS_INSN_LSLR_W_R, CRIS_INSN_LSLR_D_R - , CRIS_INSN_LSLQ, CRIS_INSN_BTST, CRIS_INSN_BTSTQ, CRIS_INSN_SETF - , CRIS_INSN_CLEARF, CRIS_INSN_RFE, CRIS_INSN_SFE, CRIS_INSN_RFG - , CRIS_INSN_RFN, CRIS_INSN_HALT, CRIS_INSN_BCC_B, CRIS_INSN_BA_B - , CRIS_INSN_BCC_W, CRIS_INSN_BA_W, CRIS_INSN_JAS_R, CRIS_INSN_JUMP_R - , CRIS_INSN_JAS_C, CRIS_INSN_JUMP_M, CRIS_INSN_JUMP_C, CRIS_INSN_JUMP_P - , CRIS_INSN_BAS_C, CRIS_INSN_JASC_R, CRIS_INSN_JASC_C, CRIS_INSN_BASC_C - , CRIS_INSN_BREAK, CRIS_INSN_BOUND_R_B_R, CRIS_INSN_BOUND_R_W_R, CRIS_INSN_BOUND_R_D_R - , CRIS_INSN_BOUND_M_B_M, CRIS_INSN_BOUND_M_W_M, CRIS_INSN_BOUND_M_D_M, CRIS_INSN_BOUND_CB - , CRIS_INSN_BOUND_CW, CRIS_INSN_BOUND_CD, CRIS_INSN_SCC, CRIS_INSN_LZ - , CRIS_INSN_ADDOQ, CRIS_INSN_BDAPQPC, CRIS_INSN_BDAP_32_PC, CRIS_INSN_MOVE_M_PCPLUS_P0 - , CRIS_INSN_MOVE_M_SPPLUS_P8, CRIS_INSN_ADDO_M_B_M, CRIS_INSN_ADDO_M_W_M, CRIS_INSN_ADDO_M_D_M - , CRIS_INSN_ADDO_CB, CRIS_INSN_ADDO_CW, CRIS_INSN_ADDO_CD, CRIS_INSN_DIP_M - , CRIS_INSN_DIP_C, CRIS_INSN_ADDI_ACR_B_R, CRIS_INSN_ADDI_ACR_W_R, CRIS_INSN_ADDI_ACR_D_R - , CRIS_INSN_BIAP_PC_B_R, CRIS_INSN_BIAP_PC_W_R, CRIS_INSN_BIAP_PC_D_R, CRIS_INSN_FIDXI - , CRIS_INSN_FTAGI, CRIS_INSN_FIDXD, CRIS_INSN_FTAGD -} CGEN_INSN_TYPE; - -/* Index of `invalid' insn place holder. */ -#define CGEN_INSN_INVALID CRIS_INSN_INVALID - -/* Total number of insns in table. */ -#define MAX_INSNS ((int) CRIS_INSN_FTAGD + 1) - -/* This struct records data prior to insertion or after extraction. */ -struct cgen_fields -{ - int length; - long f_nil; - long f_anyof; - long f_operand1; - long f_size; - long f_opcode; - long f_mode; - long f_operand2; - long f_memmode; - long f_membit; - long f_b5; - long f_opcode_hi; - long f_dstsrc; - long f_u6; - long f_s6; - long f_u5; - long f_u4; - long f_s8; - long f_disp9_hi; - long f_disp9_lo; - long f_disp9; - long f_qo; - long f_indir_pc__byte; - long f_indir_pc__word; - long f_indir_pc__word_pcrel; - long f_indir_pc__dword; - long f_indir_pc__dword_pcrel; -}; - -#define CGEN_INIT_PARSE(od) \ -{\ -} -#define CGEN_INIT_INSERT(od) \ -{\ -} -#define CGEN_INIT_EXTRACT(od) \ -{\ -} -#define CGEN_INIT_PRINT(od) \ -{\ -} - - -#endif /* CRIS_OPC_H */