From: Luke Kenneth Casson Leighton Date: Thu, 21 May 2020 11:57:20 +0000 (+0100) Subject: move common functionality between PipeSpecs to soc.fu.pipe_data X-Git-Tag: div_pipeline~993 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=547ab8078a5e4c68fd762395f3353bbc68d1513f;p=soc.git move common functionality between PipeSpecs to soc.fu.pipe_data --- diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py index 768d6a44..42bea516 100644 --- a/src/soc/fu/alu/pipe_data.py +++ b/src/soc/fu/alu/pipe_data.py @@ -1,7 +1,6 @@ from nmigen import Signal, Const -from nmutil.dynamicpipe import SimpleHandshakeRedir from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.fu.pipe_data import IntegerData +from soc.fu.pipe_data import IntegerData, CommonPipeSpec from ieee754.fpcommon.getop import FPPipeContext from soc.decoder.power_decoder2 import Data @@ -62,12 +61,6 @@ class ALUOutputData(IntegerData): self.xer_ov.eq(i.xer_ov), self.xer_so.eq(i.xer_so)] -class ALUPipeSpec: +class ALUPipeSpec(CommonPipeSpec): regspec = (ALUInputData.regspec, ALUOutputData.regspec) opsubsetkls = CompALUOpSubset - def __init__(self, id_wid, op_wid): - self.pipekls = SimpleHandshakeRedir - self.id_wid = id_wid - self.op_wid = op_wid - self.opkls = lambda _: self.opsubsetkls(name="op") - self.stage = None diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index dbdb4f6e..52ba0fa4 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -24,13 +24,6 @@ class TestCase: self.sprs = sprs self.name = name -def get_rec_width(rec): - recwidth = 0 - # Setup random inputs for dut.op - for p in rec.ports(): - width = p.width - recwidth += width - return recwidth def set_alu_inputs(alu, dec2, sim): # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 @@ -163,9 +156,7 @@ class ALUTestCase(FHDLTestCase): self.run_tst_program(Program(lst), initial_regs, {}) def test_ilang(self): - rec = ALUPipeSpec.opsubsetkls() - - pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) + pspec = ALUPipeSpec(id_wid=2) alu = ALUBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open("alu_pipeline.il", "w") as f: @@ -186,9 +177,7 @@ class TestRunner(FHDLTestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) - rec = ALUPipeSpec.opsubsetkls() - - pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) + pspec = ALUPipeSpec(id_wid=2) m.submodules.alu = alu = ALUBasePipe(pspec) comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e) diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py index 80b601e1..ad12d56f 100644 --- a/src/soc/fu/branch/pipe_data.py +++ b/src/soc/fu/branch/pipe_data.py @@ -26,8 +26,7 @@ from nmigen import Signal, Const from ieee754.fpcommon.getop import FPPipeContext from soc.decoder.power_decoder2 import Data -from soc.fu.pipe_data import IntegerData -from nmutil.dynamicpipe import SimpleHandshakeRedir +from soc.fu.pipe_data import IntegerData, CommonPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace @@ -91,12 +90,6 @@ class BranchOutputData(IntegerData): # TODO: replace CompALUOpSubset with CompBranchOpSubset -class BranchPipeSpec: +class BranchPipeSpec(CommonPipeSpec): regspec = (BranchInputData.regspec, BranchOutputData.regspec) opsubsetkls = CompALUOpSubset - def __init__(self, id_wid, op_wid): - self.id_wid = id_wid - self.op_wid = op_wid - self.opkls = lambda _: self.opsubsetkls(name="op") - self.stage = None - self.pipekls = SimpleHandshakeRedir diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index 75cac809..77bcdc02 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -11,7 +11,6 @@ from soc.decoder.selectable_int import SelectableInt from soc.simulator.program import Program from soc.decoder.isa.all import ISA - from soc.fu.branch.pipeline import BranchBasePipe from soc.fu.branch.pipe_data import BranchPipeSpec import random @@ -98,9 +97,7 @@ class BranchTestCase(FHDLTestCase): initial_cr=cr) def test_ilang(self): - rec = BranchPipeSpec.opsubsetkls() - - pspec = BranchPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) + pspec = BranchPipeSpec(id_wid=2) alu = BranchBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open("branch_pipeline.il", "w") as f: @@ -121,9 +118,7 @@ class TestRunner(FHDLTestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) - rec = BranchPipeSpec.opsubsetkls() - - pspec = BranchPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) + pspec = BranchPipeSpec(id_wid=2) m.submodules.branch = branch = BranchBasePipe(pspec) comb += branch.p.data_i.ctx.op.eq_from_execute1(pdecode2.e) diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py index 7a9e4422..3bfdd6fa 100644 --- a/src/soc/fu/cr/pipe_data.py +++ b/src/soc/fu/cr/pipe_data.py @@ -1,7 +1,6 @@ from nmigen import Signal, Const from ieee754.fpcommon.getop import FPPipeContext -from soc.fu.pipe_data import IntegerData -from nmutil.dynamicpipe import SimpleHandshakeRedir +from soc.fu.pipe_data import IntegerData, CommonPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace @@ -42,12 +41,6 @@ class CROutputData(IntegerData): self.cr.eq(i.cr)] # TODO: replace CompALUOpSubset with CompCROpSubset -class CRPipeSpec: +class CRPipeSpec(CommonPipeSpec): regspec = (CRInputData.regspec, CROutputData.regspec) opsubsetkls = CompALUOpSubset - def __init__(self, id_wid, op_wid): - self.id_wid = id_wid - self.op_wid = op_wid - self.opkls = lambda _: self.opsubsetkls(name="op") - self.stage = None - self.pipekls = SimpleHandshakeRedir diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py index 31da5496..e022ed6f 100644 --- a/src/soc/fu/cr/test/test_pipe_caller.py +++ b/src/soc/fu/cr/test/test_pipe_caller.py @@ -26,14 +26,6 @@ class TestCase: self.name = name self.cr = cr -def get_rec_width(rec): - recwidth = 0 - # Setup random inputs for dut.op - for p in rec.ports(): - width = p.width - recwidth += width - return recwidth - # This test bench is a bit different than is usual. Initially when I # was writing it, I had all of the tests call a function to create a @@ -117,9 +109,7 @@ class CRTestCase(FHDLTestCase): def test_ilang(self): - rec = CRPipeSpec.opsubsetkls() - - pspec = CRPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) + pspec = CRPipeSpec(id_wid=2) alu = CRBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open("cr_pipeline.il", "w") as f: @@ -149,9 +139,7 @@ class TestRunner(FHDLTestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) - rec = CRPipeSpec.opsubsetkls() - - pspec = CRPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) + pspec = CRPipeSpec(id_wid=2) m.submodules.alu = alu = CRBasePipe(pspec) comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e) diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py index eb012713..27e2a694 100644 --- a/src/soc/fu/logical/pipe_data.py +++ b/src/soc/fu/logical/pipe_data.py @@ -1,8 +1,7 @@ from nmigen import Signal, Const from ieee754.fpcommon.getop import FPPipeContext from soc.fu.pipe_data import IntegerData -from soc.fu.alu.pipe_data import ALUOutputData -from nmutil.dynamicpipe import SimpleHandshakeRedir +from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace @@ -33,12 +32,6 @@ class LogicalInputData(IntegerData): # TODO: replace CompALUOpSubset with CompLogicalOpSubset -class LogicalPipeSpec: +class LogicalPipeSpec(CommonPipeSpec): regspec = (LogicalInputData.regspec, ALUOutputData.regspec) opsubsetkls = CompALUOpSubset - def __init__(self, id_wid, op_wid): - self.id_wid = id_wid - self.op_wid = op_wid - self.opkls = lambda _: self.opsubsetkls(name="op") - self.stage = None - self.pipekls = SimpleHandshakeRedir diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py index a676e8f6..073aad72 100644 --- a/src/soc/fu/logical/test/test_pipe_caller.py +++ b/src/soc/fu/logical/test/test_pipe_caller.py @@ -24,15 +24,6 @@ class TestCase: self.name = name -def get_rec_width(rec): - recwidth = 0 - # Setup random inputs for dut.op - for p in rec.ports(): - width = p.width - recwidth += width - return recwidth - - def set_alu_inputs(alu, dec2, sim): # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) @@ -179,9 +170,7 @@ class LogicalTestCase(FHDLTestCase): self.run_tst_program(Program(lst), initial_regs) def test_ilang(self): - rec = LogicalPipeSpec.opsubsetkls() - - pspec = LogicalPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) + pspec = LogicalPipeSpec(id_wid=2) alu = LogicalBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open("logical_pipeline.il", "w") as f: @@ -202,9 +191,7 @@ class TestRunner(FHDLTestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) - rec = LogicalPipeSpec.opsubsetkls() - - pspec = LogicalPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) + pspec = LogicalPipeSpec(id_wid=2) m.submodules.alu = alu = LogicalBasePipe(pspec) comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e) diff --git a/src/soc/fu/pipe_data.py b/src/soc/fu/pipe_data.py index 764de09f..3ceab14a 100644 --- a/src/soc/fu/pipe_data.py +++ b/src/soc/fu/pipe_data.py @@ -1,4 +1,5 @@ from ieee754.fpcommon.getop import FPPipeContext +from nmutil.dynamicpipe import SimpleHandshakeRedir class IntegerData: @@ -15,3 +16,21 @@ class IntegerData: def ports(self): return self.ctx.ports() + +# hmmm there has to be a better way than this +def get_rec_width(rec): + recwidth = 0 + # Setup random inputs for dut.op + for p in rec.ports(): + width = p.width + recwidth += width + return recwidth + + +class CommonPipeSpec: + def __init__(self, id_wid): + self.pipekls = SimpleHandshakeRedir + self.id_wid = id_wid + self.opkls = lambda _: self.opsubsetkls(name="op") + self.op_wid = get_rec_width(self.opkls(None)) # hmm.. + self.stage = None diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py index 29f07efc..8b0139e1 100644 --- a/src/soc/fu/shift_rot/pipe_data.py +++ b/src/soc/fu/shift_rot/pipe_data.py @@ -2,7 +2,7 @@ from nmigen import Signal, Const from nmutil.dynamicpipe import SimpleHandshakeRedir from soc.fu.alu.alu_input_record import CompALUOpSubset from ieee754.fpcommon.getop import FPPipeContext -from soc.fu.pipe_data import IntegerData +from soc.fu.pipe_data import IntegerData, CommonPipeSpec from soc.fu.alu.pipe_data import ALUOutputData from nmutil.dynamicpipe import SimpleHandshakeRedir @@ -38,12 +38,6 @@ class ShiftRotInputData(IntegerData): # TODO: replace CompALUOpSubset with CompShiftRotOpSubset -class ShiftRotPipeSpec: +class ShiftRotPipeSpec(CommonPipeSpec): regspec = (ShiftRotInputData.regspec, ALUOutputData.regspec) opsubsetkls = CompALUOpSubset - def __init__(self, id_wid, op_wid): - self.id_wid = id_wid - self.op_wid = op_wid - self.opkls = lambda _: self.opsubsetkls(name="op") - self.stage = None - self.pipekls = SimpleHandshakeRedir diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index 595d5a3b..713ebd61 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -181,9 +181,7 @@ class ShiftRotTestCase(FHDLTestCase): self.run_tst_program(Program(lst), initial_regs) def test_ilang(self): - rec = ShiftRotPipeSpec.opsubsetkls() - - pspec = ShiftRotPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) + pspec = ShiftRotPipeSpec(id_wid=2) alu = ShiftRotBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open("pipeline.il", "w") as f: @@ -204,9 +202,7 @@ class TestRunner(FHDLTestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) - rec = ShiftRotPipeSpec.opsubsetkls() - - pspec = ShiftRotPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) + pspec = ShiftRotPipeSpec(id_wid=2) m.submodules.alu = alu = ShiftRotBasePipe(pspec) comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)