From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Tue, 7 Jul 2020 09:10:09 +0000 (+0100)
Subject: dev-arm: Move GICv2 intConfig for consistency
X-Git-Tag: v20.1.0.0~483
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=548e2884ec4f56d8a420d725d5f7d40740c690bc;p=gem5.git

dev-arm: Move GICv2 intConfig for consistency

Every other helper is placed below the respective array storage

JIRA: https://gem5.atlassian.net/browse/GEM5-667

Change-Id: I398ac23eb68d84a8e0ed856550bfac8e403a86b3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31054
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 4ef15173d..321337937 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -72,7 +72,7 @@ GicV2::GicV2(const Params *p)
       enabled(false), haveGem5Extensions(p->gem5_extensions),
       itLines(p->it_lines),
       intEnabled {}, pendingInt {}, activeInt {},
-      intPriority {}, cpuTarget {}, intConfig {},
+      intPriority {}, intConfig {}, cpuTarget {},
       cpuSgiPending {}, cpuSgiActive {},
       cpuSgiPendingExt {}, cpuSgiActiveExt {},
       cpuPpiPending {}, cpuPpiActive {},
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 600f9afa8..40a95539c 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -281,6 +281,10 @@ class GicV2 : public BaseGic, public BaseGicRegisters
         }
     }
 
+    /** 2 bit per interrupt signaling if it's level or edge sensitive
+     * and if it is 1:N or N:N */
+    uint32_t intConfig[INT_BITS_MAX*2];
+
     /** GICD_ICFGRn
      * get 2 bit config associated to an interrupt.
      */
@@ -319,10 +323,6 @@ class GicV2 : public BaseGic, public BaseGicRegisters
         }
     }
 
-    /** 2 bit per interrupt signaling if it's level or edge sensitive
-     * and if it is 1:N or N:N */
-    uint32_t intConfig[INT_BITS_MAX*2];
-
     bool isLevelSensitive(ContextID ctx, uint32_t ix) {
         if (ix == SPURIOUS_INT) {
             return false;