From: rishucoding <rishucoding@gmail.com>
Date: Mon, 9 Jul 2018 10:50:07 +0000 (+0530)
Subject: Merge branch 'master' of libre-riscv.org:/pinmux
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=549565dc4eadb02f49dc9656bc11a4aff33e90aa;p=pinmux.git

Merge branch 'master' of libre-riscv.org:/pinmux
---

549565dc4eadb02f49dc9656bc11a4aff33e90aa
diff --cc src/test_bsv/tests/test_pinmux.py
index 3a2fec1,84e8aa6..08761de
--- a/src/test_bsv/tests/test_pinmux.py
+++ b/src/test_bsv/tests/test_pinmux.py
@@@ -398,9 -399,9 +399,9 @@@ def pinmux_twi_sda3(dut)
      # Test for out for twi_sda
      if dut.iocell_side_io1_cell_out != 0:
          raise TestFailure(
 -            "twi_sda=0/mux=0/out=1 %s iocell_io1 != 0" %
 +            "twi_sda=0/mux=2/out=1 %s iocell_io1 != 0" %
              str(dut.iocell_side_io1_cell_out))
-     
+ 
      dut.peripheral_side_twi_sda_out_in = 1
      yield Timer(2)
      # ok, now io1_cell_out should be equal to 1
@@@ -445,19 -446,19 +446,19 @@@
  
      if dut.peripheral_side_twi_sda_out_in != 1:  # output of twi_sda
          raise TestFailure(
 -            "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 0" %
 +            "twi_sda=0/mux=0/out=1 %s iocell_io0 != 0" %
              str(dut.iocell_side_io2_cell_out))
  
-     # Now, let's test the working of output muxing logic 
-     # at cell1. First, the output of io1_cell_out should 
-     # be the previous value (1). 
+     # Now, let's test the working of output muxing logic
+     # at cell1. First, the output of io1_cell_out should
+     # be the previous value (1).
  
      yield Timer(2)
      if dut.iocell_side_io1_cell_out != 1:
          raise TestFailure(
 -            "twi_sda=1/mux=0/out=1 %s iocell_io1 != 1" %
 +            "twi_sda=1/mux=2/out=1 %s iocell_io1 != 1" %
              str(dut.iocell_side_io1_cell_out))
-    
+ 
      # ok, now set the muxing selection line for gpio1
      # again, the value of gpio_out_in should be 0
      # ie. opposite of twi_sda_out