From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 2 Jun 2010 17:58:06 +0000 (-0500)
Subject: ARM: Decode the ssub instructions.
X-Git-Tag: stable_2012_02_02~1275
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5495ebd68d10e9472543dcd9c95e8b5a7a58a36b;p=gem5.git

ARM: Decode the ssub instructions.
---

diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index 28fb50194..648e04453 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -240,11 +240,11 @@ def format ArmParallelAddSubtract() {{
                   case 0x2:
                     return new WarnUnimplemented("ssax", machInst);
                   case 0x3:
-                    return new WarnUnimplemented("ssub16", machInst);
+                    return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL);
                   case 0x4:
                     return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL);
                   case 0x7:
-                    return new WarnUnimplemented("ssub8", machInst);
+                    return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL);
                 }
                 break;
               case 0x2:
@@ -557,12 +557,14 @@ def format Thumb32DataProcReg() {{
                           case 0x6:
                             return new WarnUnimplemented("ssax", machInst);
                           case 0x5:
-                            return new WarnUnimplemented("ssub16", machInst);
+                            return new Ssub16RegCc(machInst, rd,
+                                                   rn, rm, 0, LSL);
                           case 0x0:
                             return new Sadd8RegCc(machInst, rd,
                                                   rn, rm, 0, LSL);
                           case 0x4:
-                            return new WarnUnimplemented("ssub8", machInst);
+                            return new Ssub8RegCc(machInst, rd,
+                                                  rn, rm, 0, LSL);
                         }
                         break;
                       case 0x1: