From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 15 May 2021 17:04:54 +0000 (+0100)
Subject: add fcpsgn unit test
X-Git-Tag: 0.0.3~21
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=549b8f0f5b6657fdfbaf0c063ae306258d726096;p=openpower-isa.git

add fcpsgn unit test
---

diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index 3fff1dfb..26c68721 100644
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -122,6 +122,26 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(5), SelectableInt(0xC040266660000000, 64))
             self.assertEqual(sim.fpr(6), SelectableInt(0xC040266660000000, 64))
 
+    def test_fp_sgn(self):
+        """>>> lst = ["fcpsgn 3, 1, 2",
+                      "fcpsgn 4, 2, 1",
+                     ]
+        """
+        lst = ["fcpsgn 3, 1, 2",
+               "fcpsgn 4, 2, 1",
+                     ]
+
+        fprs = [0] * 32
+        fprs[1] = 0xC040266660000001
+        fprs[2] = 0x4040266660000000
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_fprs=fprs)
+            self.assertEqual(sim.fpr(1), SelectableInt(0xC040266660000001, 64))
+            self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
+            self.assertEqual(sim.fpr(3), SelectableInt(0xC040266660000000, 64))
+            self.assertEqual(sim.fpr(4), SelectableInt(0x4040266660000001, 64))
+
     def run_tst_program(self, prog, initial_regs=None,
                               initial_mem=None,
                               initial_fprs=None):